STR-A6100 Ver la hoja de datos (PDF) - Sanken Electric co.,ltd.
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STR-A6100 Datasheet PDF : 26 Pages
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STR-A6100 Series
10.2 PCB Trace Layout and Component
Placement
Since the PCB circuit trace design and the component
layout significantly affects operation, EMI noise, and
power dissipation, the high frequency PCB trace should
be low impedance with small loop and wide trace.
In addition, the ground traces affect radiated EMI
noise, and wide, short traces should be taken into
account.
Figure 10-5 shows the circuit design example.
(1) Main Circuit Trace Layout: S/OCP pin to ROCP to C1
to T1 (winding P) to D pin
This is the main trace containing switching currents,
and thus it should be as wide trace and small loop as
possible. If C1 and the IC are distant from each other,
placing a capacitor such as film capacitor (about 0.1
μF and with proper voltage rating) close to the
transformer or the IC is recommended to reduce
impedance of the high frequency current loop.
(2) Control Ground Trace Layout
Since the operation of IC may be affected from the
large current of the main trace that flows in control
ground trace, the control ground trace should be
separated from main trace and connected at a single
point grounding of point A in Figure 10-5 as close
to the ROCP pin as possible.
(3) VCC Trace Layout: GND pin to C2 (negative) to T1
(winding D) to R2 to D2 to C2 (positive) to VCC pin
This is the trace for supplying power to the IC, and
thus it should be as small loop as possible. If C2 and
the IC are distant from each other, placing a
capacitor such as film capacitor Cf (about 0.1 μF to
1.0 μF) close to the VCC pin and the GND pin is
recommended.
(4) ROCP Trace Layout
ROCP should be placed as close as possible to the
S/OCP pin. The connection between the power
ground of the main trace and the IC ground should
be at a single point ground (point A in Figure
10-5) which is close to the base of ROCP.
(5) FB/OLP Trace Layout
The components connected to FB/OLP pin should be
as close to FB/OLP pin as possible. The trace
between the components and FB/OLP pin should be
as short as possible.
(6) Secondary Rectifier Smoothing Circuit Trace
Layout: T1 (winding S) to D51 to C51
This is the trace of the rectifier smoothing loop,
carrying the switching current, and thus it should be
as wide trace and small loop as possible. If this trace
is thin and long, inductance resulting from the loop
may increase surge voltage at turning off the power
MOSFET. Proper rectifier smoothing trace layout
helps to increase margin against the power MOSFET
breakdown voltage, and reduces stress on the clamp
snubber circuit and losses in it.
(7) Thermal Considerations
Because the power MOSFET has a positive thermal
coefficient of RDS(ON), consider it in thermal design.
Since the copper area under the IC and the D pin
trace act as a heatsink, its traces should be as wide as
possible.
STR-A6100 - DS Rev.2.1
SANKEN ELECTRIC CO.,LTD.
20
Jun. 05, 2014
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