STK12C68-W25(1999) Ver la hoja de datos (PDF) - Unspecified
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STK12C68-W25 Datasheet PDF : 12 Pages
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STK12C68
SRAM WRITE CYCLES #1 & #2
(VCC = 5.0V ± 10%)b, f
SYMBOLS
NO.
#1
#2
Alt.
PARAMETER
STK12C68-20 STK12C68-25 STK12C68-35 STK12C68-45
UNITS
MIN MAX MIN MAX MIN MAX MIN MAX
12
tAVAV
tAVAV
tWC Write Cycle Time
20
25
35
45
ns
13
tWLWH
tWLEH
tWP Write Pulse Width
15
20
25
30
ns
14
tELWH
tELEH
tCW Chip Enable to End of Write
15
20
25
30
ns
15
tDVWH
tDVEH
tDW Data Set-up to End of Write
8
10
12
15
ns
16
tWHDX
tEHDX
tDH Data Hold after End of Write
0
0
0
0
ns
17
tAVWH
tAVEH
tAW Address Set-up to End of Write
15
20
25
30
ns
18
tAVWL
tAVEL
tAS Address Set-up to Start of Write
0
0
0
0
ns
19
tWHAX
20
tWLQZ j, k
tEHAX
tWR Address Hold after End of Write
0
0
0
0
ns
tWZ Write Enable to Output Disable
7
10
13
15
ns
21
tWHQX
tOW Output Active after End of Write
5
5
5
5
ns
Note k: If W is low when E goes low, the outputs remain in the high-impedance state.
Note l: E or W must be ≥ VIH during address transitions.
Note m: HSB must be high during SRAM WRITE cycles.
SRAM WRITE CYCLE #1: W Controlledl, m
ADDRESS
E
12
tAVAV
14
tELWH
19
tWHAX
18
tAVWL
W
17
tAVWH
13
tWLWH
DATA IN
DATA OUT
20
tWLQZ
PREVIOUS DATA
15
tDVWH
DATA VALID
HIGH IMPEDANCE
SRAM WRITE CYCLE #2: E Controlledl, m
ADDRESS
E
18
tAVEL
12
tAVAV
14
tELEH
16
tWHDX
21
tWHQX
19
tEHAX
W
DATA IN
DATA OUT
17
tAVEH
13
tWLEH
15
tDVEH
DATA VALID
HIGH IMPEDANCE
16
tEHDX
July 1999
4-44
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