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T8100-BAL

Ambassador™ T8100 H.100/H.110 Interface and Time-Slot Interchanger

Agere -> LSI Corporation 

Advisory

March 1999

AmbassadorTM T8100

H.100/H.110 Interface and Time-Slot Interchanger

This advisory details two changes to the AmbassadorTM T8100 H.100/H.110 Interface and Time-Slot

Interchanger Preliminary Data Sheet: DS98-195NTNB.

Change Affecting Page 15, Section 2.1.3 Address Mode Register

Problem:

There is a minor bug in the T8100. If a write is issued to the address mode register (AMR)

address 0x70 (local bus, holding registers, and reset), the T8100’s RDY line gets stuck low (not

ready state).

Workaround: To solve this, issue another write command to any of the four direct registers (MCR, LAR,

AMR, or IDR) and the RDY signal will reset.

Change Affecting Page 38, Section 2.4.2 Dividers and Rate Multipliers

There is an anomaly in the digital phase-lock loop (DPLL) performance of the device. The behavior affects all

versions of the T8100 but has been corrected in the T8100A, T8102, and T8105. This anomaly affects applica-

tions that use the DPLL for CT bus clock generation.

When used for clocking, the DPLL uses the 16.384 MHz internal oscillator to rate multiply an 8 kHz input sig-

nal. In order for the DPLL to lock to the 8.000000 kHz signal, the required internal oscillator frequency range

should be centered at 16.388 MHz. A frequency of 16.384 MHz is too low for the DPLL to perform properly.

If this crystal adaptation is used for the DPLL, there are several limitations. First, do not select the crystal as a

fallback clock source. When the crystal is a clock source, the generated clocks are all multiples of the crystal. In

that case, they will be offset by the same ratio as the crystal. Second, do not use TCLKOUT. It is also derived

from the crystal and will be offset by the same ratio. Third, the watchdogs will be slightly more sensitive due to

the increased clock frequency. In designs affected by these limitations, conversion to the T8100A is recom-

mended.

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