SPT774C Ver la hoja de datos (PDF) - Cadeka Microcircuits LLC.
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Fabricante
SPT774C Datasheet PDF : 12 Pages
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The analog and digital common pins should be tied together
as close to the package as possible to guarantee best
performance. The code dependent currents flow through the
VDD terminal and not through the analog and digital common
pins.
RANGE CONSIDERATIONS
The SPT774 may be operated by a microprocessor or in the
stand-alone mode. The part has four standard input ranges:
0 V to +10 V, 0 V to +20 V, ±5 V and ±10 V. The maximum
errors that are listed in the specifications for gain and offset
may be adjusted externally to zero as explained in the next
two sections.
CALIBRATION & CONNECTION PROCEDURES
UNIPOLAR
The calibration procedure consists of adjusting the
converter’s most negative output to its ideal value for offset
adjustment and then adjusting the most positive output to its
ideal value for gain adjustment.
Starting with offset adjustment and referring to figure 5, the
midpoint of the first LSB increment should be positioned at
the origin to get an output code of all 0s. To do this, an input
of +1/2 LSB or +1.22 mV for the 10 V range and +2.44 mV for
the 20 V range should be applied to the SPT774. Adjust the
offset potentiometer R1 for code transition flickers between
0000 0000 0000 and 0000 0000 0001.
The gain adjustment should be done at positive full scale. The
ideal input corresponding to the last code change is applied.
This is 1 and 1/2 LSB below the nominal full scale which is
+9.9963 V for the 10 V range and +19.9927 V for the 20 V
range. Adjust the gain potentiometer R2 for flicker between
codes 1111 1111 1110 and 1111 1111 1111. If calibration is
not necessary for the intended application, replace R2 with a
50 Ω, 1% metal film resistor and remove the network from the
BIP OFF pin. Connect the BIP OFF pin to AGND. Connect the
analog input to the 10 V IN pin for the 0 to 10 V range or to the
20 V IN pin for the 0 to 20 V range.
BIPOLAR
The gain and offset errors listed in the specification may be
adjusted to zero using the potentiometers R1 and R2. (See
figure 6.) If adjustment is not needed, either or both pots may
be replaced by a 50 Ω, 1% metal film resistor.
To calibrate, connect the analog input signal to the 10 V IN pin
for a ±5 V range or to the 20 V IN pin for a ±10 V range. First
apply a DC input voltage 1/2 LSB above negative full scale
which is -4.9988 V for the ±5 V range or -9.9976 V for the ±10
V range. Adjust the offset potentiometer R1 for flicker be-
tween output codes 0000 0000 0000 and 0000 0000 0001.
Next, apply a DC input voltage 1 and 1/2 LSB below positive
full scale which is +4.9963 V for the ±5 V range or +9.9927 V
for the ±10 V range. Adjust the gain potentiometer R2 for
flicker between codes 1111 1111 1110 and 1111 1111 1111.
Figure 5 - Unipolar Input Connections
Figure 6 - Bipolar Input Connections
Output Bits
R/C
CS
Ao
12/8
CE
-15 V
R1
100 kΩ
+15 V
100 kΩ
100 Ω
0 to 10 V
Analog
Inputs
0 to 20 V
10 V In
20 V In
BIP Off
VRef Out
100 Ω
R2
(Calibration)
VRef In
Control
Logic
Oscillator
Nibble A
Nibble B
Nibble C
Three-State Buffers And Control
12-Bits
12-Bit SAR
12-Bits
Strobe
Sample/Hold
MSB
CDAC
LSB
Comp
STS
VDD
.1 µF
DGND
Ref
Ref
Amp
Offset/Gain
Trim Network
VEE
+5 V
Output Bits
R/C
CS
Nibble A
Nibble B
Nibble C
Control
Ao
Logic
Three-State Buffers And Control
12/8
CE
12-Bits
Oscillator
12-Bit SAR
±5 V
Analog
Inputs
±10 V
100 Ω
R1
10 V In
20 V In
BIP Off
VRef Out
12-Bits
Strobe
Sample/Hold
MSB
CDAC
LSB
Comp
Ref
Ref
Amp
Offset/Gain
Trim Network
STS
VDD
.1 µF
DGND
+5 V
100 Ω
R1
VRef In
VEE
SPT774
7
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