SPT7610 Ver la hoja de datos (PDF) - Cadeka Microcircuits LLC.
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SPT7610 Datasheet PDF : 10 Pages
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DIGITAL OUTPUTS: D0 TO D6, DR, NDR (A AND B)
The digital outputs can drive 50 Ω to ECL levels when
pulled down to –2 V. When pulled down to –5.2 V, the out-
puts can drive 130 Ω to 1 kΩ loads. CADEKA recommends
using differential receivers on the outputs of the data
ready lines to ensure the proper output rise and fall times.
BINARY AND TWO’S COMPLEMENT OUTPUT:
MINV, LINV
Control pins are provided that enable selection of one of
four digital output formats. (Table I shows selection of
these output formats as a function of the MINV and LINV
pins.) When the MINV pin is high, the MSB output is in-
verted and when it is low, the it is noninverted. Likewise,
when the LINV pin is high, the LSB output is inverted and
when it is low, the it is noninverted. The user can select
either binary, inverted binary, two’s complement or
inverted two’s complement digital output format.
REFERENCE INPUTS: VRBF, VRBS, VR1, VRM,
VR3, VRTF, VRTS
There are two reference inputs and three external refer-
ence voltage taps. These are –1.0 V VRBF (bottom force)
and VRBS (bottom sense), –0.75 V VR1 (1/4 tap), –0.5 V
VRM (mid-point tap), –0.25 V VR3 (3/4 tap) and 0.0 V
(AGND) VRTF (top force) and VRTS (top sense). The top ref-
erence pin is normally tied to analog ground (AGND) and
the bottom reference pin can be driven by an op amp as
shown in figure 3.
ladder taps are typically bypassed to add noise suppres-
sion as shown in figure 3 or may be driven with op amps to
adjust integral linearity.
SPT7610 TEST MODE FUNCTION: TEST PIN
The SPT7610 supports a special test mode function that
overrides the SPT7610’s internal data output latch stage
and exercises the digital outputs in an alternating test pat-
tern. This enables the user to test digital interface logic
downstream from the SPT7610 with a known set of digital
test patterns.
Test mode pin 3 controls the SPT7610 mode of operation
such that when it is low, the SPT7610 operates in normal
mode. When test mode pin 3 is brought high, the
SPT7610 will begin to output test pattern 1 (table II) on the
next rising edge of the clock. (See figure 2.) It will output
the test patterns alternating between test pattern 1 and
test pattern 2 as long as test mode pin 3 is held high. The
minimum set-up time (tsu) can be as low as 0 nsec.
Only the digital output stage is involved in the test mode
operation. All ADC stages before the digital output stage
continue normal data conversion operation while the test
mode is active. When test mode pin 3 is brought back low,
the SPT7610 will resume output of valid data on the next
rising edge of the clock. The valid data output will corre-
spond to a two-clock-cycle pipeline delay as shown in
figure 2.
Table II – SPT7610 Test Mode Output Bit Patterns
The reference voltage taps can be used to control integral
linearity over temperature. The mid-point reference tap
(VRM) is normally driven by an op amp to insure tempera-
ture stable operation or may be bypassed for limited tem-
perature operation. The 1/4 (VR1) and 3/4 (VR3) reference
Test Pattern 1
Test Pattern 2
D6 D5 D4 D3 D2 D1 D0
1010101
0101010
Table I – Output Coding Table
ANALOG INPUT VOLTAGE D6
–1 V + 1/2 LSB
0
0
–0.5 V
0
0 V – 1/2 LSB
0
1
0V
1
BINARY
TWOs COMPLEMENT
TRUE
INVERTED
TRUE
INVERTED
MINV=LINV=0 MINV=LINV=1 MINV=1; LINV=0 MINV=0; LINV=1
D5_______D0 D5______D0
D5______D0
D5______D0
000000
111111
1000000
0111111
000001
111110
1000001
0111110
0111111
100000
111111
000000
100000
011111
000000
111111
111111
000000
011111
100000
111111
000000
011111
100000
111111
000000
011111
100000
1 Tie MINV/LINV to GND for logic 1.
2 Float MINV/LINV for logic 0. (MINV/LINV are internally pulled down to –5.2 V.)
SPT7610
7
1/21/02
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