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ST20-GP6

GPS PROCESSOR

STMicroelectronics 

ST20-GP6

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 ST20-GP6 architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Digital signal processing module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1 DSP module registers ........................................................................................................................... 13

4 Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1 Registers ............................................................................................................................................... 19

4.2 Processes and concurrency ................................................................................................................. 20

4.3 Priority ................................................................................................................................................... 22

4.4 Process communications ...................................................................................................................... 23

4.5 Timers ................................................................................................................................................... 23

4.6 Traps and exceptions ........................................................................................................................... 24

5 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.1 Interrupt vector table ............................................................................................................................. 31

5.2 Interrupt handlers .................................................................................................................................. 31

5.3 Interrupt latency .................................................................................................................................... 32

5.4 Preemption and interrupt priority .......................................................................................................... 32

5.5 Restrictions on interrupt handlers ......................................................................................................... 33

5.6 Interrupt configuration registers ............................................................................................................ 33

6 Interrupt level controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.1 Interrupt assignments ........................................................................................................................... 37

6.2 Interrupt level controller registers ......................................................................................................... 37

7 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.1 Instruction cycles .................................................................................................................................. 40

7.2 Instruction characteristics ..................................................................................................................... 41

7.3 Instruction set tables ............................................................................................................................. 42

8 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

8.1 System memory use ............................................................................................................................. 51

8.2 Boot ROM ............................................................................................................................................. 52

8.3 Internal peripheral space ...................................................................................................................... 52

9 Memory subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

9.1 SRAM ................................................................................................................................................... 55

9.2 ROM ..................................................................................................................................................... 55

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