SCANPSC100FSCX Ver la hoja de datos (PDF) - Fairchild Semiconductor
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SCANPSC100FSCX Datasheet PDF : 21 Pages
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Parallel Processor Interface (PPI) (Continued)
READ AND WRITE CYCLES
be successfully completed without the use of the RDY sig-
A Write cycle (see Figure 2) is initiated by asserting CE
and R/W low followed by a LOW on STB a set time later.
CE and STB are gated within the PSC100F and may be
asserted concurrently (i.e., zero setup and hold time). The
address is then asserted on A2:0 to indicate which internal
address within the PSC100F will be written to by the pro-
cessor. An address decoder within the PSC100F monitors
the address lines for a valid PSC100F register address.
Once a valid address has been decoded, the RDY line
becomes active (a propagation delay time later). The active
RDY line will go LOW immediately if the addressed register
is ready to accept data. If the addressed register is not
ready, the RDY pin will remain HIGH preventing the pro-
cessor from completing the bus cycle. Once the register is
ready to receive date (see Table 2), the RDY pin will go
LOW and processor can resume the write cycle. The pro-
cessor then forces a HIGH on STB (a wait time after RDY
goes LOW) which latches the address (A2:0) and data
(D7:0) completing the bus cycle. The RDY line is forced
HIGH a propagation delay later.
A Read cycle (see Figure 3) is initiated by asserting CE
LOW and R/W HIGH followed by a LOW on STB a set time
later. CE and STB are gated within the PSC100F and may
be asserted concurrently (i.e., zero setup and hold time).
The address bits (A2:0) are then asserted to indicate which
internal address within the PSC100F will be read by the
processor. An address decoder within the PSC100F moni-
nal. All read and write cycles will complete within 2.5 SCK
cycles (worst case). Therefore, by assuring at least 2.5
cycles occur after the rising edge of STB, bus cycles can
be completed without using the RDY “handshake”. The crit-
ical timing relationship within the PSC100F for write and
read operation is between the rising edge of STB and the
falling edge of SCK. The rising edge of strobe latches the
address/data and also generates the internal signals
required to complete read/write within the PSC100F
(including a signal with resets the read/write logic and
releases the RDY line). The propagation of these internal
signals is initiated on the first falling edge of SCK after the
STB pin is asserted HIGH. If the rising edge on STB occurs
an internal setup time (tS4) or greater before the falling
edge of SCK, the bus cycle can be completed within 1.5
SCK cycles (see Figure 4). However, if the internal setup
time is not met, the propagation of internal control/reset
signals is delayed until the next falling edge of SCK (1 SCK
cycle later) which effectively completes the read/write oper-
ation and reset the logic for the next bus cycle within 2.5
cycles (see Figure 5). Synchronizing the rising edge of STB
with the falling edge of SCK to assure that tS4 is met pro-
vides the maximum performance for a read/write operation.
However, the asynchronous interface can be used effec-
tively with software delays, hardware delays or pro-
grammed wait states (to assure 2.5 SCK cycles are
completed) to avoid the need for synchronization.
tors the address lines for a valid PSC100F register
address. Once a valid address has been decoded and if
the addressed PSC100F register is ready to be read (see
Table 2), valid data is placed on the Data lines (D7:0) a
propagation delay later and the ready line is asserted LOW.
If the addressed register is not ready (e.g., the TDI shifter/
buffer is empty), the ready line will remain HIGH and hold
the bus cycle until the register contains valid data. RDY will
Consecutive Reads and Writes: Separate control logic
and data/address latches are used for a read and write
operation within the PSC100F. This allows a write to occur
after a read (or conversely, a read to occur after a write)
prior to the 1.5/2.5 SCK clock cycle requirements
described above. The timing for a read (or write) followed
by a write (or read) is shown in Figure 5 and Figure 6.
then go LOW allowing the read cycle to continue. With the SYNCHRONIZATION
HIGH-to-LOW edge on RDY line, the processor can suc-
cessfully read the valid data. However, the bus cycle is not
completed within the PSC100F until the rising edge on STB
which resets the PSC100F read logic (required prior to the
start of the next read cycle).
Important note concerning the use of RDY: The RDY
signal provides a useful “handshake” between the
PSC100F and the processor. However, care must be taken
when using the PSC100F RDY signal to prevent a large (or
indefinite) number of processor generated wait states. For
example, if the TDO shifter/buffer is not enabled for shift
operations and the processor writes to the TDO shifter/
buffer address 3 times, the two registers which make up
Writes and reads can be synchronized by using any of
three methods: polling, interrupts, or wait state generation:
• Status bits may be polled to see if a register is ready to
be written to or read from. To stabilize the status bits for
read operations, the Update Status bit must be set in
MODE2 to latch the status.
Note: The status bits only provide the state of the shifter/buffers and do not
indicate that an internal write or read is complete. Therefore, for applica-
tions not using the RDY signal to monitor the internal write/read status, tim-
ing must be controlled to assure that at least 2.5 SCK cycles are completed
between consecutive read or consecutive write cycles.
• Any of three different events can be used to generate
interrupts by forcing the INT pin HIGH, see Table 1.
the TDO shifter/buffer will accept the first two bytes of data,
but since the data is not shifting out, the 3rd byte will be
held off by the RDY signal indefinitely. An equally severe
problem could result with a finite number of wait states if
the application uses dynamic memories. Holding the local
bus with the PSC100F RDY line long enough to violate a
DRAM refresh time will result in lost data within the
dynamic memory.
• The RDY pin can be used to hold off the host until the
addressed register is ready to be accessed. As
described above, this pin can also be used to hold off
additional reads/writes until the synchronizer has recov-
ered from the previous read/write. RDY = 0 signifies that
the SCANPSC100F is ready to complete the current PPI
cycle. The logic that determines the state of RDY is
summarized in Table 2.
Writing and Reading without the use of RDY: With use
of worst case PSC100F timing, Write and Read cycles can
Reading from CNT32 can be synchronized for testing by
using the Single Step Counter mode bit.
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