SCANPSC100FSCX Ver la hoja de datos (PDF) - Fairchild Semiconductor

Número de pieza

componentes Descripción

Fabricante

SCANPSC100FSCX

Embedded Boundary Scan Controller (IEEE 1149.1 Support)

Fairchild Semiconductor 

Pin Descriptions

Pin Name

Description

RST (Input)

SCK (Input)

The Reset pin is an asynchronous input that, when LOW, initializes the SCANPSC100. Mode bits,

Shifter/Buffer and CNT32 control logic, TCK Control, and the PPI are all initialized to defined states.

RST has hysteresis for improved noise immunity.

The System Clock drives all internal timing. The test clock, TCK, is a gated and buffered version of SCK.

SCK has hysteresis for improved immunity.

OE (Input)

Output Enable 3-STATEs all SSI outputs when HIGH. A 20 kΩ pull-up resistor is connected to

automatically 3-STATE these outputs when this signal is floating.

CE (Input)

Chip Enable, when LOW, enables the PPI for byte transfers. D(7:0) and RDY are 3-STATEd if CE is HIGH.

CE has hysteresis for improved noise immunity.

R/W (Input)

STB (Input)

A(2:0) (Input)

D(7:0) (I/O)

INT (Output)

Read/Write defines a PPI cycle—Read when HIGH, Write when LOW.

R/W has hysteresis for improved noise immunity.

Strobe is used for timing all PPI byte transfers. D(7:0) are 3-STATEd when STB is HIGH. All other PPI

inputs must meet specified setup and hold times with respect to this signal. STB has hysteresis for noise

improved immunity.

The Address pins are used to select the register to be written to or read from.

Bidirectional pins used to transfer parallel data to and from the SCANPSC100.

Interrupt is used to trigger a host interrupt for any of the defined interrupt events. INT is active HIGH.

RDY

Ready is used to synchronize asynchronous byte transfers between the host and the SCANPSC100.

(3-STATE Output) When LOW, RDY signals that the addressed register is ready to be accessed RDY is enabled when

CE is LOW

TDO

Test Data Out is the serial scan output from the SCANPSC100. TDO is enabled when OE is LOW.

(3-STATE Output)

TMS(1:0)

The Test Mode Select pins are serial outputs used to supply control logic to the UUT.

(3-STATE Output) TMS(1:0) are enabled when OE is LOW.

TCK

The Test Clock output is a buffered version of SCK for distribution in the UUT.

(3-STATE Output) TCK Control logic starts and stops TCK to prevent overflow and underflow conditions.

TCK is enabled when OE is LOW.

TDI (Input)

Test Data In is the serial scan input to the SCANPSC100. A 20 kΩ pull-up resistor is connected to force

TDI to a logic 1 when the TDO line from the UUT is floating.

FRZ (Input)

The Freeze pin is used to asynchronously generate a user-specific pulse on TCK. If the FRZ Enable Mode

bit is set, TCK will be forced HIGH if FRZ goes HIGH. FRZ has hysteresis for improved noise immunity.

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