SCANPSC100FSCX Ver la hoja de datos (PDF) - Fairchild Semiconductor
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SCANPSC100FSCX Datasheet PDF : 21 Pages
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Serial Scan Interface (SSI) (Continued)
TMS(1:0) SHIFTER/BUFFERS
The TMS Shifter/Buffer block diagram is shown in Figure
10. These two blocks take parallel data and serialize it for
shift operations through the serial port pins TMS0 and
TMS1.
Double-buffering is achieved by configuring the shifter/
buffer as a 2 x 8 FIFO. Write and shift operations are con-
trolled by a local state machine that accepts stimulus from
the PPI, Mode Registers, CNT32 and TCK Control section.
The TMS outputs always change on the falling edge of
SCK. The order of shifting is least significant bit first.
TMS(1:0) are forced HIGH upon RST LOW. TMS(1:0) are
3-STATEd when OE is HIGH.
Write operations are completed if the shifter/buffer is not
full (independent of whether shifter/buffer is enabled or dis-
abled). Otherwise they are ignored. Shifting occurs when
the following conditions are all true:
• TMS is enabled with its respective mode bit.
• TMS shifter/buffer is not empty.
• TCK is enabled according to the logic in TCK Control.
When shift operations are not enabled, the TMS output
retains its last state. During long shift sequences, the TMS
shifter/buffer can be disabled and held static so that shift
operations are concentrated only on TDI and TDO. The
TMS output also retains its last state when Test Loop-Back
operations are in progress.
Local select circuitry is used to toggle back and forth
between the two registers of the “FIFO” when shifting. At
any given time, one register is selected for shift operations.
The other holds its previous state or can accept new paral-
lel data. Shift register selection changes due to the follow-
ing two events:
• CNT3 in TCK Control signals that 8 bits have been
shifted. This event is used for basic toggling between
each of the two shift registers.
• CNT32 enabled and at terminal count. This event is
used to account for scan lengths which are not multiples
of eight. When shift register selection changes due to
this signal, any data remaining in the shift register is
unused.
AUTO TMS HIGH MODE. This feature is included in the
TMS shifter/buffer block to improve the efficiency of the
PSC100 in supporting shift operations within the 1149.1
devices connected to the SSI. Shifting data and instruc-
tions into 1149.1 compliant devices requires that their TAP
controllers be sequenced to the Shift-DR or Shift-IR states
(see Figure 8). Once in this state, shifting occurs by holding
TMS LOW and clocking TCK. The last bit is shifted when
the TAP controller transitions to the EXIT1 state. This tran-
sition requires a logic 1 on TMS. The Auto TMS High fea-
ture, enabled by setting bit 1 of Mode Register 0,
automatically creates a logic 1 on the TMS lines of the
PSC100 when CNT32 = 1. Consequently, the last bit is
shifted out without having to load specific TMS data into
the shifter/buffer.
Note: Auto TMS High mode creates a logic 1 on both TMS lines (i.e., TMS0
and TMS1). Therefore, when using the Auto TMS High feature, all 1149.1
devices connected to the TMS line not participating in the current JTAG test
operations should be placed in the Test-Logic-Reset TAP controller state to
prevent inadvertent TAP controller transitions.
TDO SHIFTER/BUFFER
The TDO Shifter/Buffer block diagram is shown in Figure
11. This block takes parallel data and serializes it for shift
operations through the serial port pin TDO. During normal
shift modes, double-buffering is achieved by configuring
the shifter/buffer as a 2 x 8 FIFO. This block can also be
configured as a 32-bit Pseudo Random Pattern Generator
(PRPG) with two additional 8-bit parallel-to-serial shift reg-
isters. Write and shift operations are controlled by a local
state machine that accepts stimulus from the PPI, Mode
Registers, CNT32, and the TCK Control section. The TDO
output always changes on the falling edge of SCK. The
order of shifting is least significant bit first. TDO is forced
high upon RST LOW. TDO is 3-STATEd when OE is HIGH.
Write operations are completed if the shifter/buffer is not
full (independent of whether shifter/buffer is enabled or dis-
abled). Otherwise they are ignored.
Shifting occurs when the following conditions are all true:
• TDO is enabled with its respective mode bit.
• TDO shifter/buffer is not empty.
• TCK is enabled according to the logic in TCK Control.
When shift operations are not enabled, the TDO output
retains its last state. The TDO output also retains its last
state when Test Loop-Back operations are in progress.
Local select circuitry is used to toggle back and forth
between the two registers of the “FIFO” when shifting. At
any given time, one register is selected for shift operations.
The other holds its previous state or can accept new paral-
lel data. Shift register selection changes due to the follow-
ing two events:
• CNT3 in TCK Control signals that 8 bits have been
shifted. This event is used for basic toggling between
each of the two shift registers.
• CNT32 enabled and at terminal count. This event is
used to account for scan lengths which are not multiples
of eight. When shift register selection changes due to
this signal, any data remaining in the shift register is
unused.
PRPG MODE. By setting MODE1(4), the TDO Shifter/
Buffer is reconfigured as a 32-bit PRPG (Pseudo Random
Pattern Generator) using the primitive polynomial:
F(X) = X32 + X22 + X2 + X + 1
The PSC100 was developed to support both 1149.1 and
non-1149.1 serial test methodologies. Since 1149.1 compli-
ant devices include boundary scan registers on control pins
(i.e. OE), which must remain fixed during boundary scan
interconnect testing, generating pseudo-random patterns
with PRPG mode provides limited usefulness for boundary
scan test operations. PRPG mode may provide usefulness
in other serial test or non-test related implementations
which do not require fixed bits in the serial chain.
Figure 12 shows a block diagram of the Linear Feedback
Shift Register hookup.
11
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