QL2009 Ver la hoja de datos (PDF) - Unspecified

Número de pieza

componentes Descripción

Fabricante

QL2009

3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility

Unspecified 

QL2009

PIN DESCRIPTIONS

Pin

Function

Description

TDI

Test Data In for JTAG

Hold HIGH during normal operation. Connect to

VCC if not used for JTAG.

TRSTB

Active low Reset for JTAG

Hold LOW during normal operation. Connect to

ground if not used for JTAG.

TMS

Test Mode Select for JTAG

Hold HIGH during normal operation. Connect to

VCC if not used for JTAG.

TCK

Test Clock for JTAG

Hold HIGH or LOW during normal operation.

Connect to VCC or ground if not used for JTAG.

3

TDO

Test data out for JTAG

Output that must be left unconnected if not used for JTAG.

STM

Special Test Mode

Must be grounded during normal operation.

I/ACLK

High-drive input and/or array

network driver

Can be configured as either or both.

I/GCLK

High-drive input and/or global

network driver

Can be configured as either or both.

I

High-drive input

Use for input signals with high fanout.

I/O

Input/Output pin

Can be configured as an input and/or output.

VCC

Power supply pin

Connect to 3.3V supply.

GND

Ground pin

Connect to ground.

QuickLogic

pASIC device

pASIC 2 device

part number

Speed Grade

X = quick

0 = fast

1 = faster

2 = fastest

QL 2009 - 1 PQ208 C

Operating Range

C = Commercial

I = Industrial

Package Code

PF144 = 144-pin TQFP

PQ208 = 208-pin PQFP

PB256 = 256-pin PBGA

ORDERING

INFORMATION

3-41

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