PEB20321 Ver la hoja de datos (PDF) - Siemens AG
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PEB20321 Datasheet PDF : 326 Pages
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PEB 20321
Introduction
– V.110/X.30 Protocol
– Automatic synchronization in receive direction, automatic generation of
the synchronization pattern in transmit direction
– E/S/X bits freely programmable in transmit direction, may be changed
during transmission; changes monitored and reported in receive direction
– Generation/detection of loss of synchronism
– Bit framing with network data rates from 600 bit/s up to 38.4 Kbit/s
– Transparent Mode A
– Slot synchronous transparent transmission/reception without frame structure
– Flag generation, flag stuffing, flag extraction, flag generation
in the abort case with programmable flag
– Synchronized data transfer for fractional T1/PRI channels
– Transparent Mode B
– Transparent transmission/reception in frames delimited by 00H flags
– Shared opening and closing flag
– Flag stuffing, flag detection, flag generation in the abort case
– Error detection (non octet frame content, short frame, long frame)
– Transparent Mode R
– Transparent transmission/reception with GSM 08.60 frame structure
– Automatic 0000H flag generation/detection
– Support of 40, 391/2, 401/2 octet frames
– Error detection (non octet frame contents, short frame, long frame)
– Protocol Independent
– Channel inversion (data, flags, IDLE code)
– Format conventions as in CCITT Q.921 § 2.8
– Data over- and underflow detected
• Microprocessor Interface
– 32-bit PCI bus interface option, 33 MHz
– 32-bit De-multiplexed bus interface option, 33 MHz
– 68 channel DMA controller (64 for 32 serial channels, 4 for 2 LBI channels) with
buffer chaining capability
– Master 4-DWORD burst read and write capability
– Slave single-DWORD read and write capability
– Interrupt-circular buffers with variable sizes
– Maskable interrupts for each channel
• IOM®-2 Interface with on-chip C/I and monitor handlers
• Synchronous Serial Control (SSC) Interface
• 8-/16-bit Local Bus Interface (LBI)
Semiconductor Group
9
1998-08-01
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