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NIS3001

Integrated Driver and MOSFET Power Chip for Synchronous Buck Controllers

ON Semiconductor 

NIS3001

several DRN pins available, it is recommended that pin 14

be used because of its proximity to the BST pin.

Drain Pin: The DRN pin is also called the switch node.

It is the connection between the source of the top FET and

the drain of the bottom FET. This node is connected to one

terminal of the output filter inductor. When the top FET is

conducting, the DRN pin is essentially connected to the 12

volt source. When the bottom FET is conducting, this node

is essentially connected to ground. When the driver is

disabled, this node is in a high impedance state, and is

essentially connected to neither.

Top Gate Pin: The TG pin is the internal connection of

the output of the high−side driver and also the gate of the

top FET. There is normally no connection to this pin. It can

however, be used to drive an external FET which will

operate in parallel with the top FET.

This pin may also be attached to the pcb for additional

heat sinking or used to monitor the top gate waveform.

Bottom Gate Pin: The BG pin is the internal connection

of the output of the lower driver and bottom FET gate.

There is normally no connection to this pin, although it may

be used for paralleling an additional FET, monitoring or

heat sinking, similar to the TG pin.

Power Ground: The PGND pin is the power ground for

the device. The source of the bottom FET is also connected

to this pin. This pin is not internally connected to the GND

pin and care should be taken when laying out the circuit to

maintain proper isolation between these grounds.

Signal Ground: The GND pin is the ground pin for the

driver, and is internally isolated from the PGND pin.

Layout Considerations

While the design of the NIS3001 reduces many of the

parasitic elements when compared to a discrete solution,

careful consideration to layout must still be observed. The

following suggestions are offered:

a) Mount the bootstrap capacitor very close to the

package. Use DRN pin 14 and BST pin 17 due to

their proximity. The capacitor should be a high

quality ceramic type.

b) Mount the VS pin bypass capacitor as close as

possible to the package. This should be a high

quality ceramic capacitor and is mounted

between pins 4 and 2.

c) VIN requires a combination of bypass capacitors.

These consist of both low ESR aluminum

electrolytics and high quality ceramics. The

ceramics should be SMT devices and mounted as

close to the VIN and PGND pins as possible. The

aluminum capacitors are generally located

slightly farther away, but should be connected via

power and ground planes to maintain the lowest

possible impedance. The total amount of

capacitance required is dependant on the system

requirements.

d) Keep as much copper area as possible on all

layers in the proximity of the device for best

thermal performance. Especially, keep large

copper areas connected to the large pads on the

chip, and use thermal vias to transmit the heat to

the bottom side of the board when possible.

e) All vias underneath the chip, whether thermal or

not should be plugged with epoxy or some

material other than solder. The amount of solder

paste used for mounting is important to a good

connection. Empty vias can siphon off solder

during the mounting process and leave voids,

while soldered vias may contribute solder and

cause shorts below the chip.

f) Power and ground (PGND) busses should be

distributed through power and ground planes.

These should feed through vias to the appropriate

pads for the 12 volts, switch node and ground

connections. The impedances of the high current

paths are critical for optimum efficiency.

5V +

−

BST

VS

TG

VIN

EN

DRIVER

DRN

CO

GND

BG

PGND

+

12 V

−

VOUT

RL

Figure 15.

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