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NIS3001

Integrated Driver and MOSFET Power Chip for Synchronous Buck Controllers

ON Semiconductor 

NIS3001

INTRODUCTION

The NIS3001 represents a significant improvement in

high frequency power conversion, by combining a high

performance driver with two power MOSFET devices for

use in synchronous buck converters. All three die are

assembled in a QFN package called a PInPAK.

This approach minimizes the parasitic elements in the

power path by reducing the distance between the three

devices. The leadless design also provides an excellent

thermal path for the removal of heat which is generated

during the power conversion process. All of these

improvements result in a higher conversion efficiency

when operation at high frequencies (350 kHz to 1000 kHz)

is required. Operating at higher frequencies, reduces the

number of electrolytic capacitors and the size of filter

inductors required to meet load line and transient response

requirements.

This device is designed to process power from a nominal

12 V source (ranging from 7 V to 14 V), while obtaining its

internal bias power from a 5 V supply. The output voltage

can range from 0.7 V to 5.1 V with a maximum duty cycle

of 50%. It requires signal inputs from a synchronous buck

controller, such as the NCP5316.

A minimum number of external components are required

to create a complete power converter. Figure 15 is an

example of a simplified solution.

Operational Description

Driver: The internal driver requires a nominal 5 volt bias

voltage to operate. The bootstrap voltage is normally

derived from this same source. The bootstrap circuit

typically employs a schottky diode as part of the charge

pump that provides the isolated supply voltage to the high

side driver.

The driver uses several control functions to provide the

correct gate drive signals. The control (CO) input accepts

the drive signal from the synchronous converter PWM. The

driver circuitry programs a delay between the top and

bottom FETs, such that they will not conduct at the same

time.

An enable pin (EN) allows the output of the driver to be

shut down by a logic level signal. In this mode of operation,

the bias current is reduced to a level of 10 mA. When the

driver is disabled, the gates of both FETs are low and the

drain (DRN) output of the NIS3001 is in a high impedance

state.

To guarantee system integrity, the driver also

incorporates an internal UVLO circuit. It is activated when

the bias voltage reaches 4.25 volts, and will shut down the

driver when if the bias voltage drops below 3.975 volts. In

the UVLO shutdown condition, both FETs are off, and the

DRN pin is in a high impedance state.

Power MOSFETs: The NIS3001 contains two power

FETs which are directly connected to the internal driver

chip. They have different on resistances and are designed

for optimum performance for current VRM voltage and

current requirements. The drain of the top FET is

connected to the 12 volt input and the source is connected

to the DRN pins. The drain of the bottom FET is also

connected to the DRN pins, while its source is connected

to the power ground pins.

Functional Pin Description

VS Pin: The VS pin connects to a nominal 5 volt supply

and provides power to the driver chip. It is necessary to

provide a bypass capacitor between 1.0 mF and 10.0 mF in

close proximity to this pin and the ground (GND) pin. This

capacitor allows a low impedance path for the high

frequency currents that occur when the gate of the bottom

FET switches. The voltage at this pin is monitored

internally by the UVLO circuit which will disable the

driver if there is not sufficient voltage available to assure

proper operation of the driver.

VIN Pin: The VIN pin connects to the nominal 12 volt

supply which provides power to the switching stage of the

converter. It connects to the drain of the top FET, which is

the controlled switch of the buck converter. This pin needs

a combination of electrolytic and ceramic capacitors for

bypass purposes.

Enable Pin: The EN pin accepts a logic level signal that

can both source and sink current. There is no hysteresis on

the signal switching levels for this pin, so care should be

taken that the high and low logic levels of the driving signal

should be above and below the switching points by several

hundred millivolts.

In its high state, the driver is operational and will respond

to inputs on the CO pin. In its low state, the driver is

disabled. In this state, it enters a reduced power mode and

turns off both FETs, thereby providing a high impedance

output at the DRN pin.

A bypass capacitor is not normally required for the

enable signal.

Control Pin: The CO pin accepts a logic signal from the

PWM output of the controller chip. This signal is fed into

the driver and controls the top and bottom FETs. When this

pin is in a high state, the top FET is fully enhanced and the

bottom FET is not conducting. When the signal is low, the

bottom FET is fully enhanced and the top FET is not

conducting.

During the switching transition, there is a non−overlap

control circuit that is designed to provide optimum

switching timing for the two FETs. This circuit eliminates

the possibility of cross conduction, by monitoring the

voltage on the DRN pin to time the turn−on of the bottom

FET.

Bootstrap Pin: The BST pin connects to an external

diode−capacitor circuit that acts as a charge pump to

provide a floating, isolated voltage source for the high−side

driver. A schottky diode is recommended, which charges

the capacitor when the DRN pin is low. This diode is

normally connected to the same source as the VS pin.

The capacitor (typically 0.2 to 1.0 mF) is connected from

the BST to the DRN pin. The capacitor should be mounted

as close as possible to the NIS3001 package. As there are

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