MX29F8100 Ver la hoja de datos (PDF) - Macronix International
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MX29F8100 Datasheet PDF : 37 Pages
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INDEX
MX29F8100
Table1.PIN DESCRIPTIONS
SYMBOL
A0 - A18
Q0 - Q7
Q8 - Q14
.Q15/A -1
CE1/CE2
PWD
OE
WE
RY/BY
WP
BYTE
VCC
GND
TYPE
INPUT
INPUT/OUTPUT
INPUT/OUTPUT
INPUT/OUTPUT
INPUT
INPUT
INPUT
INPUT
OPEN DRAIN
OUTPUT
INPUT
INPUT
NAME AND FUNCTION
ADDRESS INPUTS: for memory addresses. Addresses are internally latched
during a write cycle, A19 don't care.(hard wired to VCC or GND is suggested)
LOW-BYTE DATA BUS: Input data and commands during Command Interface
Register(CIR) write cycles. Outputs array,status and identifier data in the
appropriate read mode. Floated when the chip is de-selected or the outputs are
disabled.
HIGH-BYTE DATA BUS: Inputs data during x 16 Data-Write operations. Outputs
array, identifier data in the appropriate read mode; not used for status register
reads. Floated when the chip is de-selected or the outputs are disabled
Selects between high-byte data INPUT/OUTPUT(BYTE = HIGH) and LSB
ADDRESS(BYTE = LOW)
CHIP ENABLE INPUTS: Activate the device's control logic, Input buffers,
decoders and sense amplifiers. With either CE1 or CE2 high, the device is de-
selected and power consumption reduces to Standby level upon completion of
any current program or erase operations. Both CE1,CE2 must be low to
select the device. CE2 is not provided in 44-pin SOP package.
All timing specifications are the same for both signals. Device selection occurs
with the latter falling edge of CE1 or CE2. The first rising edge of CE1 or CE2
disables the device.
POWER-DOWN: Puts the device in deep power-down mode. PWD is active low;
PWD high gates normal operation. PWD also locks out erase or program
operation when active low providing data protection during power transitions.
OUTPUT ENABLES: Gates the device's data through the output buffers during
a read cycle OE is active low.
WRITE ENABLE: Controls writes to the Command Interface Register(CIR).
WE is active low.
READY/BUSY: Indicates the status of the internal Write State Machine(WSM).
When low it indicates that the WSM is performing a erase or program operation.
RY/BY high indicate that the WSM is ready for new commands, sector erase is
suspended or the device is in deep power-down mode. RY/BY is always active
and does not float to tristate off when the chip is deselected or data output are
disabled.
WRITE PROTECT: Top or Bottom sector can be protected by writing a non-
volatile protect-bit for each sector. When WP is high, all sectors can be
programmed or erased regardless of the state of the protect-bits. The WP input
buffer is disabled when PWD transitions low(deep power-down mode).
BYTE ENABLE: BYTE Low places device in x8 mode. All data is then input or
output on Q0-7 and Q8-14 float. AddressQ15/A-1 selects between the high
and low byte. BYTE high places the device in x16 mode, and turns off the Q15/
A-1 input buffer. Address A0, then becomes the lowest order address.
DEVICE POWER SUPPLY(5V±10%)
GROUND
P/N: PM0262
REV. 2.0, JAN. 22, 1999
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