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MX27C1000DC-45

1M-BIT [128K x 8] CMOS EPROM

Macronix International 

INDEX

MX27C1000/1001

PROGRAM INHIBIT MODE

Programming of multiple MX27C1000/1001s in parallel

with different data is also easily accomplished by using

the Program Inhibit Mode. Except for CE and OE, all

like inputs of the parallel MX27C1000/1001 may be

common. A TTL low-level program pulse applied to an

MX27C1000/1001 CE input with VPP = 12.5 ± 0.5 V and

PGM LOW will program that MX27C1000/1001. A high-

level CE input inhibits the other MX27C1000/1001s from

being programmed.

PROGRAM VERIFY MODE

Verification should be performed on the programmed bits

to determine that they were correctly programmed. The

verification should be performed with OE and CE at VIL,

PGM at VIH, and VPP at its programming voltage.

AUTO IDENTIFY MODE

The auto identify mode allows the reading out of a binary

code from an EPROM that will identify its manufacturer

and device type. This mode is intended for use by

programming equipment for the purpose of automatically

matching the device to be programmed with its

corresponding programming algorithm. This mode is

functional in the 25°C ± 5°C ambient temperature range

that is required when programming the MX27C1000/

1001.

To activate this mode, the programming equipment must

force 12.0 ± 0.5 V on address line A9 of the device. Two

identifier bytes may then be sequenced from the device

outputs by toggling address line A0 from VIL to VIH. All

other address lines must be held at VIL during auto

identify mode.

Byte 0 ( A0 = VIL) represents the manufacturer code,

and byte 1 (A0 = VIH), the device identifier code. For

the MX27C1000/1001, these two identifier bytes are

given in the Mode Select Table. All identifiers for

manufacturer and device codes will possess odd parity,

with the MSB (DQ7) defined as the parity bit.

READ MODE

The MX27C1000/1001 has two control functions, both

of which must be logically satisfied in order to obtain data

at the outputs. Chip Enable (CE) is the power control

and should be used for device selection. Output Enable

(OE) is the output control and should be used to gate

data to the output pins, independent of device selection.

Assuming that addresses are stable, address access time

(tACC) is equal to the delay from CE to output (tCE). Data

is available at the outputs tQE after the falling edge of

OE, assuming that CE has been LOW and addresses

have been stable for at least tACC - tQE.

STANDBY MODE

The MX27C1000/1001 has a CMOS standby mode which

reduces the maximum VCC current to 100 uA. It is placed

in CMOS standby when CE is at VCC ± 0.3 V. The

MX27C1000/1001 also has a TTL-standby mode which

reduces the maximum VCC current to 1.5 mA. It is placed

in TTL-standby when CE is at VIH. When in standby

mode, the outputs are in a high-impedance state,

independent of the OE input.

TWO-LINE OUTPUT CONTROL FUNCTION

To accommodate multiple memory connections, a two-

line control function is provided to allow for:

1. Low memory power dissipation,

2. Assurance that output bus contention will not occur.

It is recommended that CE be decoded and used as the

primary device-selecting function, while OE be made a

common connection to all devices in the array and

connected to the READ line from the system control bus.

This assures that all deselected memory devices are in

their low-power standby mode and that the output pins

are only active when data is desired from a particular

memory device.

SYSTEM CONSIDERATIONS

During the switch between active and standby conditions,

transient current peaks are produced on the rising and

falling edges of Chip Enable. The magnitude of these

transient current peaks is dependent on the output

capacitance loading of the device. At a minimum, a 0.1

uF ceramic capacitor (high frequency, low inherent

inductance) should be used on each device between VCC

and GND to minimize transient effects. In addition, to

overcome the voltage drop caused by the inductive effects

of the printed circuit board traces on EPROM arrays, a

4.7 uF bulk electrolytic capacitor should be used between

VCC and GND for each eight devices. The location of

the capacitor should be close to where the power supply

is connected to the array.

P/N: PM0234

REV. 5.3, MAY 07, 1998

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