MX26C4000B Ver la hoja de datos (PDF) - Macronix International
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MX26C4000B Datasheet PDF : 20 Pages
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MX26C4000B
FUNCTIONAL DESCRIPTION
When the MX26C4000B is delivered, or it is erased, the
chip has all 4M bits in the "ONE", or HIGH state.
"ZEROs" are loaded into the MX26C4000B through the
procedure of programming.
ERASE ALGORITHM
The MX26C4000B do not required preprogramming
before an erase operation. The erase algorithm is a close
loop flow to simultaneously erase all bits in the entire
array. Erase operation starts with the initial erase
operation. Erase verification begins at address 0000H
by reading data FFH from each byte. If any byte fails
to erase. the entire chip is reerased. to a maximum for
10 pulse counts of 500ms duration for each pulse. The
maximum cumulative erase time is 3s. However. the
device is usually erased in no more than 3 pulses. Erase
verification time can be reduced by storing the address
of the last byte that failed. Following the next erase
operation verification may start at the stored address
location. JEDEC standard erase algorithm can also be
used. But erase time will increase by performing the
unnecessary preprogramming.
PROGRAM ALGORITHM
The device is programmed byte by byte. A maximum
of 25 pulses. each of 100us duration is allowed for each
byte being programmed. The byte may be programmed
sequentially or by random. After each program pulse,
a program verify is done to determine if the byte has
been successfully programmed.
Programming then proceeds to the next desired byte
location. JEDEC standard program algorithms can be
used.
DATA WRITE PROTECTION
The design of the device protects against accidental
erasure or programming. The internal state machine is
automatically reset to the read mode on power-up. Using
control register architecture, alteration of memory can
only occur after completion of proper command
sequences. The command register is only active when V
is at high voltage. when V = V , the device defaults
PP
PP
PPL
to the Read Mode. Robust design features prevent
inadvertent write cycles resulting from VCC power-up and
power-down transitions or system noise. To avoid initiation
of write cycle during VCC power-up, a write cycle is locked
out for VCC less than 4V. The two- command program and
erase write sequence to the command register provide
additional software protection against spurious data
changes.
PROGRAM VERIFY MODE
Verification should be performed on the programmed bits
to determine that they were correctly programmed.
Verification should be performed with OE and CE, at
VIL, and VPP at its programming voltage.
ERASE VERIFY MODE
Verification should be performed on the erased chip to
determine that the whole chip(all bits) was correctly
erased. Verification should be performed with OE and
CE at VIL, and VCC = 5V, VPP = 12.5V
AUTO IDENTIFY MODE
The auto identify mode allows the reading out of a binary
code from MTP EPROM that will identify its
manufacturer and device type. This mode is intended
for use by programming equipment for the purpose of
automatically matching the device to be programmed
with its corresponding programming algorithm. This
mode is functional in the 25°C ± 5°C ambient temperature
range that is required when programming the
MX26C4000B.
To activate this mode, the programming equipment must
force 12.0 ± 0.5 V on address line A9 of the device.
Two identifier bytes may then be sequenced from the
device outputs by toggling address line A0 from VIL
to VIH. All other address lines must be held at VIL
during auto identify mode.
Byte 0 ( A0 = VIL) represents the manufacturer code,
and byte 1 (A0 = VIH), the device identifier code. For
the MX26C4000B, these two identifier bytes are given
in the Mode Select Table. All identifiers for manufacturer
and device codes will possess odd parity, with the MSB
(DQ7) defined as the parity bit.
P/N: PM0768
3
REV. 0.6, JAN. 14, 2002
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