MX26C1000B Ver la hoja de datos (PDF) - Macronix International

Número de pieza

componentes Descripción

Fabricante

MX26C1000B

1M-BIT [128K x 8] CMOS MULTIPLE-TIME-PROGRAMMABLE-EPROM

Macronix International 

MX26C1000B

EPROMTM is built on an innovative cell concept in which

over erasing the memory cell is impossible.

DATA WRITE PROTECTION

The design of the device protects against accidental

erasure or programming. The internal state machine is

automatically reset to the read mode on power-up. Using

control register architecture, alteration of memory can

only occur after completion of proper command

sequences. The command register is only active when V

is at high voltage. when V = V , the device defaults

PP

PP

PPL

to the Read Mode. Robust design features prevent

inadvertent write cycles resulting from VCC power-up and

power-down transitions or system noise. To avoid initiation

of write cycle during VCC power-up, a write cycle is locked

out for VCC less than 4V. The two- command program and

erase write sequence to the command register provide

additional software protection against spurious data

changes.

PROGRAM VERIFY MODE

Verification should be performed on the programmed bits

to determine that they were correctly programmed.

Verification should be performed with OE and CE, at

VIL, WE at VIH, and VPP at its programming voltage.

ERASE VERIFY MODE

Verification should be performed on the erased chip to

determine that the whole chip(all bits) was correctly

erased. Verification should be performed with OE and

CE at VIL, WE at VIH, and VCC = 5V, VPP = 12.5V

AUTO IDENTIFY MODE

The auto identify mode allows the reading out of a binary

code from MTP EPROM that will identify its

manufacturer and device type. This mode is intended

for use by programming equipment for the purpose of

automatically matching the device to be programmed

with its corresponding programming algorithm. This

mode is functional in the 25°C ± 5°C ambient temperature

range that is required when programming the

MX26C1000B.

To activate this mode, the programming equipment must

force 12.0 ± 0.5 V on address line A9 of the device.

Two identifier bytes may then be sequenced from the

device outputs by toggling address line A0 from VIL to

VIH. All other address lines must be held at VIL during

auto identify mode.

Byte 0 ( A0 = VIL) represents the manufacturer code,

and byte 1 (A0 = VIH), the device identifier code. For

the MX26C1000B, these two identifier bytes are given

in the Mode Select Table. All identifiers for manufacturer

and device codes will possess odd parity, with the MSB

(DQ7) defined as the parity bit.

READ MODE

The MX26C1000B has two control functions, both of

which must be logically satisfied in order to obtain data

at the outputs. Chip Enable (CE) is the power control

and should be used for device selection. Output Enable

(OE) is the output control and should be used to gate

data to the output pins, independent of device selection.

Assuming that addresses are stable, address access

time (tACC) is equal to the delay from CE to output (tCE).

Data is available at the outputs tOE after the falling edge

of OE, assuming that CE has been LOW and addresses

have been stable for at least tACC - tOE.

STANDBY MODE

The MX26C1000B has a CMOS standby mode which

reduces the maximum VCC current to 100 uA. It is

placed in CMOS standby when CE is at VCC ± 0.3 V.

The MX26C1000B also has a TTL-standby mode which

reduces the maximum VCC current to 1.5 mA. It is

placed in TTL-standby when CE is at VIH. When in

standby mode, the outputs are in a high-impedance

state, independent of the OE input.

SYSTEM CONSIDERATIONS

During the switch between active and standby

conditions, transient current peaks are produced on the

rising and falling edges of Chip Enable. The magnitude

of these transient current peaks is dependent on the

output capacitance loading of the device. At a minimum,

a 0.1 uF ceramic capacitor (high frequency, low inherent

inductance) should be used on each device between

VCC and GND to minimize transient effects. In addition,

to overcome the voltage drop caused by the inductive

P/N: PM0767

4

REV. 0.7, NOV. 20, 2002

Share Link: