MU9C2480A(1998) Ver la hoja de datos (PDF) - Music Semiconductors

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MU9C2480A
(Rev.:1998)

LANCAMs®

Music Semiconductors 

OPERATIONAL CHARACTERISTICS Continued

MU9C2480A/L

will respond. If an instruction is used to unlock the daisy

chain it will work only on the Highest-Priority Match device, if

one exists. If none exists, the instruction will have no effect

except to unlock the daisy chain. To read the Status registers

of specific devices when there is no match requires the use of

the TCO DS command to set DS=PA of each device. Single

chip systems can tie /EC HIGH and read the Status register or

the /MA and /MM pins to monitor match conditions, as the

daisy chain lock-out feature is not needed in this configuration.

This removes the need to insert a NOP in the case of a no-match.

When the Control register is set to the Enhanced mode,

you can continue to write data to the Comparand register

or issue a Move to Next Free Address instruction without

first having to issue a NOP with /EC HIGH to unlock the

daisy chain after a Compare cycle with no match, as

indicated in cases 4 and 5 of Table 5b on page 12. In the

Enhanced mode, data write cycles as well as command write

cycles are enabled in all devices even when /EC is LOW.

Exceptions are data writes, moves, or VBC instructions

involving HM, which occur only in the device with the

highest match; and data writes or move instructions

involving NF, which occur only in the device with /FI LOW

and /FF HIGH. The Enhanced mode speeds up system

performance by eliminating the need to unlock the daisy chain

before Command or Data Write cycles.

Full Flag Cascading

The Full Flag daisy chain cascading is used for three purposes:

first, to allow instructions that address Next Free locations to

operate globally; second, to provide a system wide Full flag;

third, to allow the loading of the Page Address registers during

initialization using the SFF instruction. The full flag logic causes

only the device containing the first empty location to respond

to Next Free instructions such as “MOV NF,CR,V”, which will

move the contents of the Comparand register to the first empty

location in a string of devices and set that location Valid, so it

will be available for the next automatic compare. With devices

connected as in Figure 1a on page 7, the /FF output of the last

device in a string provides a full indication for the entire string.

IEEE 802.3/802.5 Format Mapping

To support the symmetrical mapping between the address

formats of IEEE 802.3 and IEEE 802.5, the LANCAM provides

a bit translation facility. Formally expressed, the nth input

bit, D(n), maps to the xth output bit, Q(x), through the

following expressions:

D(n) = Q(7–n) for 0 < n < 7,

D(n) = Q(23–n) for 8 < n < 15

Setting Control Register bit 10 and bit 9 selects whether

to persistently translate, or persistently not to translate,

the data written onto the 64-bit internal bus. The default

condition after a Reset command is not to translate the

incoming data. Figure 2 on page 8 shows the bit mapping

between the two formats.

INITIALIZING THE LANCAM

Initialization of the LANCAM is required to configure

the various registers on the device. Since a Control

register reset establishes the operating conditions shown

in Table 4 on page 10, restoration of operating conditions

better suited for the application may be required after a

reset, whether using the Control Register reset, or

the /RESET pin. When the device powers up, the memory

and registers are in an unknown state, so the /RESET pin

must be asserted to place the device in a known state.

Setting Page Address Register Values

In a vertically cascaded system, the user must set the

individual Page Address registers to unique values by

using the Page Address initialization mechanism. Each Page

Address register must contain a unique value to prevent

bus contention. This process allows individual device

selection. The Page Address register initialization works

as follows: Writes to Page Address registers are only active

for devices with /FI LOW and /FF HIGH. At initialization,

all devices are empty, thus the top device in the string will

respond to a TCO PA instruction, and load its PA register.

To advance to the next device in the string, a Set Full Flag

(SFF) instruction is used, which is also only active for the

device with /FI LOW and /FF HIGH. The SFF instruction

changes the first device’s /FF to LOW, although the device

really is empty, which allows the next device in the string to

respond to the TCO PA instruction and load its PA register.

The initialization proceeds through the chain in a similar

manner filling all the PA registers in turn. Each device must

have a unique Page Address value stored in its PA register,

or contention will result. After all the PA registers are filled,

the entire string is reset through the Control register, which

does not change the values stored in the individual PA

registers. After the reset, the Device Select registers are

usually set to FFFFH to enable operation in Case 1 of Table

5a on page 12. The Control registers and the Segment

Control registers are then set to their normal operating

values for the application.

15

Rev. 1a

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