ML145503EP Ver la hoja de datos (PDF) - LANSDALE Semiconductor Inc.

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Fabricante

ML145503EP

PCM Codec–Filter Mono–Circuit

LANSDALE Semiconductor Inc. 

ML145502, ML145503, ML145505

LANSDALE Semiconductor, Inc.

MODE CONTROL LOGIC (VSS to VDD = 4.75 V to 12.6 V, TA = – 40 to + 85°C)

Characteristic

Min

Typ

Max

Unit

VLS Voltage for TTL Mode (TTL Logic Levels Referenced to VLS)

VSS

—

VDD – 4.0

V

VLS Voltage for CMOS Mode (CMOS Logic Levels of VSS to VDD)

VDD – 0.5

—

VDD

V

Mu/A Select Voltage

Mu–Law Mode

Sign Magnitude Mode

A–Law Mode

V

VDD – 0.5

—

VDD

VAG – 0.5

—

VAG + 0.5

VSS

—

VSS + 0.5

RSI Voltage for Reference Select Input (ML145502)

3.78 V Mode VDD – 0.5

—

VDD

V

2.5 V Mode VAG – 0.5

—

VAG + 0.5

3.15 V Mode

VSS

—

VSS + 0.5

Vref Voltage for Internal or External Reference (ML145502 Only)

V

Internal Reference Mode

VSS

—

VSS + 0.5

External Reference Mode VAG + 0.5

—

VDD – 1.0

Analog Test Mode Frequency, MS = CCI (ML145502 Only)

See Pin Description; Test Modes

—

128

—

kHz

SWITCHING CHARACTERISTICS (VSS to VDD = 9.5 V to 12.6 V, TA = – 40 to + 85°C, CL = 150 pF, CMOS or TTL Mode)

Characteristic

Symbol

Min

Typ

Max

Unit

Output Rise Time

Output Fall Time

Input Rise Time

Input Fall Time

TDD

tTLH

—

30

80

ns

tTHL

—

30

80

TDE, TDC, RCE, RDC, DC, MSI, CCI

tTLH

—

—

tTHL

—

—

4

µs

4

Pulse Width

TDE Low, TDC, RCE, RDC, DC, MSI, CCI

tw

100

—

—

ns

DCLK Pulse Frequency (ML145502/05 Only)

TDC, RDC, DC

fCL

64

—

4096

kHz

CCI Clock Pulse Frequency (MSI = 8 kHz)

fCL1

—

128

—

kHz

CCI is internally tied to TDC on the ML145503, therefore, the

fCL2

—

1536

—

transmit data clock must be one of these frequencies. This pin will accept

fCL3

—

1544

—

one of these discrete clock frequencies and will compensate to produce

fCL4

—

2048

—

internal sequencing.

fCL5

—

2560

—

Propagation Delay Time

TDE Rising to TDD Low Impedance

TDE Falling to TDD High Impedance

TDC Rising Edge to TDD Data, During TDE High

TDE Rising Edge to TDD Data, During TDC High

TTL

tP1

—

CMOS

—

TTL

tP2

—

CMOS

—

TTL

tP3

—

CMOS

—

TTL

tP4

—

CMOS

—

ns

90

180

90

150

—

55

—

40

90

180

90

150

90

180

90

150

TDC Falling Edge to TDE Rising Edge Setup Time

tsu1

20

—

TDE Rising Edge to TDC Falling Edge Setup Time

tsu2

100

—

TDE Falling Edge to TDC Rising Edge to Preserve the Next TDD Data

tsu8

20

—

RDC Falling Edge to RCE Rising Edge Setup Time

tsu3

20

—

RCE Rising Edge to RDC Falling Edge Setup Time

tsu4

100

—

RDD Valid to RDC Falling Edge Setup Time

tsu5

60

—

CCI Falling Edge to MSI Rising Edge Setup Time

tsu6

20

—

MSI Rising Edge to CCI Falling Edge Setup Time

tsu7

100

—

RDD Hold Time from RDC Falling Edge

th

100

—

TDE, TDC, RCE, RDC, RDD, DC, MSI, CCI Input Capacitance

—

—

—

ns

—

ns

—

ns

—

ns

—

ns

—

ns

—

ns

—

ns

—

ns

10

pF

TDE,TDC, RCE, RDC, RDD, DC, MSI, CCI Input Current

—

± 0.01

± 10

µA

TDD Capacitance During High Impedance (TDE Low)

—

12

15

pF

TDD Input Current During High Impedance (TDE Low)

—

± 0.1

± 10.0

µA

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