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ML12202-5P

MECL PLL Components Serial Input PLL Frequency Synthesizer

LANSDALE Semiconductor Inc. 

ML12202

LANSDALE Semiconductor, Inc.

DATA ENTRY FORMAT

The three wire interface of DATA pin, CLK (clock) pin and LE (load enable) pin controls the serial data input of the 14–bit pro-

grammable reference divider plus the prescaler setting bit, and the 18–bit programmable divider. A rising edge of the clock shifts

one bit of serial data into the internal shift registers. Depending upon the level of the control bit, stored data is transferred into

the latch when load enable pin is HIGH or OPEN.

Control bit: “H” = data is transferred into 15–bit latch of programmable reference divider

“L” = data is transferred into 18–bit latch of programmable divider

WARNING: Switching CLK or DATA after the device is programmed may generate noise on the charge pump outputs which

will affect the VCO.

PROGRAMMABLE REFERENCE DIVIDER

16–bit serial data format for the programmable reference counter, “R–counter”, and prescaler select bit (SW) is shown below. If

the control bit is HIGH, data is transferred from the 15–bit shift register into the 15–bit latch which specifies the R divide ratio (8

to 16383) and the prescaler divide ratio (SW = 0 for ÷128/129, SW = 1 for ÷64/65). An R divide ratio less than 8 is prohibited.

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