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MDT2005IB

8-bit micro-controller

Micon Design Technology Corporation 

MDT2005(IB)

Instruction Code

Mnemonic

Operands

Function

Operating

Status

010111 trrrrrrr

011001 trrrrrrr

SWAPR R, t Swap halves register

INCR R, t Increment register

[R(0~3) ↔

R(4~7)]→t

R + 1→t

None

Z

011010 trrrrrrr

011011 trrrrrrr

011100 trrrrrrr

011101 trrrrrrr

INCRSZ R, t

ADDWR R, t

SUBWR R, t

Increment register, skip if zero

Add W and register

Subtract W from register

DECR R, t Decrement register

R + 1→t

W + R→t

R ﹣W→t

(R+/W+1→t)

R ﹣1→t

None

C, HC, Z

C, HC, Z

Z

011110 trrrrrrr

010010 trrrrrrr

110100 iiiiiiii

DECRSZ R, t Decrement register, skip if zero R ﹣1→t

ANDWR R, t AND W and register

R ∩ W→t

ANDWI i AND W and immediate

i ∩ W→W

None

Z

Z

010011 trrrrrrr

IORWR R, t Inclu. OR W and register

R ∪ W→t

Z

110101 iiiiiiii

IORWI i Inclu. OR W and immediate i ∪ W→W

Z

010100 trrrrrrr

XORWR R, t Exclu. OR W and register

R ⊕ W→t

Z

110110 iiiiiiii

XORWI i Exclu. OR W and immediate i ⊕ W→W

Z

011111 trrrrrrr

COMR R, t Complement register

/R→t

Z

010110 trrrrrrr

RRR R, t Rotate right register

R(n) →R(n-1), C C

→R(7), R(0)→C

010101 trrrrrrr

RLR R, t Rotate left register

R(n)→r(n+1),C→ C

R(0), R(7)→C

010000 1xxxxxxx CLRW

Clear working register

0→W

Z

010001 0rrrrrrr

0000bb brrrrrrr

0010bb brrrrrrr

CLRR R

BCR R, b

BSR R, b

Clear register

Bit clear

Bit set

0→R

0→R(b)

1→R(b)

Z

None

None

0001bb brrrrrrr

BTSC R, b Bit Test, skip if clear

Skip if R(b)=0

None

0011bb brrrrrrr

BTSS R, b Bit Test, skip if set

1000nn nnnnnnnn LCALL n Long CALL subroutine

1010nn nnnnnnnn LJUMP n Long JUMP to address

Skip if R(b)=1

n→PC,

PC+1→Stack

n→PC

None

None

None

110000 nnnnnnnn CALL n

110001 iiiiiiii

RTWI i

11001n nnnnnnnn JUMP n

Call subroutine

Return, place immediate to W

JUMP to address

n→PC,

PC+1→Stack

Stack→PC, i→W

n→PC

None

None

None

Note :

W

:

WT

:

TMODE :

CPIO :

Working register

Watchdog timer

TMODE mode register

Control I/O port register

b : Bit position

t : Target

0 : Working register

1 : General register

This specification are subject to be changed without notice. Any latest information please preview

http;//www.mdtic.com.tw

P. 6

2005/6 VER1.3

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