MC68194(2006) Ver la hoja de datos (PDF) - ON Semiconductor

Número de pieza

componentes Descripción

Fabricante

MC68194
(Rev.:2006)

Carrier Band Modem (CBM)

ON Semiconductor 

MC68194

For a 20 pF crystal load:

20 pF = C1C2/(C1 + C2)

and

C2 = 20 pF [C1/(C1 − 20 pF)]

Typical values are C1 = 60 pF and C2 = 30 pF.

It is suggested that best results will be had with close

tolerance (5%) NPO ceramic capacitors — trimming should

not be required. If trimming is necessary, a third trimming

capacitor C3 can be placed in series with the crystal.

Capacitors C1 and C2 will have to be increased in value

because the crystal load now becomes C1 and C2 and C3 in

series. For help in designing the capacitor network the user

is directed to Design of Crystal and Other Harmonic

Oscillators, B. Parzen, Wiley, 1983.

3.4.2 Parallel−Resonant, Overtone Mode Crystal

Figure 3−4 also shows the network used for overtone

mode operation. The crystal is still parallel resonant, but

must be specified for overtone (harmonic) operation at the

desired frequency. A low series resistance of less than 30 Ω

is recommended.

VCC−OSC

OVERTONE

XTAL

C1

L1

C2

FUNDAMENTAL

C1 XTAL1

XTAL2

C2

CBM

20 kΩ

Q1

TO

BUFFER

20 kΩ

C3

800 μA

GND−OSC

Figure 3−4. Crystal Oscillator Schematic Shows

Configurations For Both Overtone and

Fundamental Modes

Inductor L1 and capacitor C2 form a tank circuit that is

parallel resonant at a frequency lower than the desired

crystal harmonic but above the next lower odd harmonic. C3

= 0.01 μF is a dc blocking capacitor to ground. At the

operating frequency the tank circuit impedance will appear

capacitive; therefore, the load to the crystal is C1 in series

with the capacitive reactance of the tank circuit.

This series combination should be equal to the desired

crystal load. Typically, C2 will increase in value as

compared to the fundamental mode situation because of the

cancelling effects of L1. Again the user is directed to the

above reference for optimum selection of components.

3.4.3 External Clock Source

Figure 3−5 shows the connection used for a TTL

compatible external clock source. XTAL1 and XTAL2 are

tied together defeating transistor Q1. External resistor R1 =

2.0 kΩ assures a high level greater than 3.0 V at an input

current of 800 μA. The TTL driver must be capable of

sinking 2.5 mA.

VCC−OSC

VCC

CBM

TTL

CLOCK

OSC

2.5 mA

R1 = 2 kΩ

XTAL1

XTAL2

20 kΩ

Q1

TO

BUFFER

20 kΩ

800 μA

GND−OSC

Figure 3−5. TTL Compatible Clock Source Driving

CBM

The IEEE 802.4 for 5 Mbps or 10 Mbps data rate carrier

band requires a transmit frequency stability of ± 100 ppm

(0.01%). The external clock source must be specified for this

stability over temperature.

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