MC1141A Ver la hoja de datos (PDF) - PMD
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MC1141A Datasheet PDF : 60 Pages
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IC
Pin Name
Pin #
I/O
~CPWrite
2
I/O
CPCntrl0
20
CPCntrl1
36
CPCntrl2
22
CPCntrl3
63
I/O
HostCmd
41
I/O
HostRdy
37
Description/Functionality
I/O chip to CP chip communication write (input). This signal is connected to the ~I/OWrite pin
(CP chip) and provides a write strobe to facilitate CP to I/O chip communication.
I/O chip to CP chip communication control (mixed). These 4 signals are connected to the
corresponding I/OCntrl0-3 pins (CP chip), and provide control signals to facilitate CP to I/O
chip communication.
Host Port Command (input). This signal is asserted high to write a host command to the chip
set. It is asserted low to read or write a host data word to the chipset
Host Port Ready/Busy (output). This signal is used to synchronize communication between
the DSP and the host. HostRdy will go low (indicating host port busy) at the end of a host
command write or after the second byte of a data write or read. HostRdy will go high
(indicating host port ready) when the command or data word has been processed and the
chip set is ready for more I/O operations. All host port communications must be made with
HostRdy high (indicating ready).
Typical busy to ready cycle is 67.5 uSec, although it can be longer when host port traffic is
high.
I/O
~HostRead
51
Host Port Read data (input). Used to indicate that a data word is being read from the chip set
(low asserts read).
I/O
~HostWrite
47
Host Port Write data (input). Used to indicate that a data word or command is being written to
the chip set (low asserts write).
I/O
~HostSlct
48
Host Port Select (input). Used to select the host port for reading or writing operations (low
assertion selects port). ~HostSlct must remain inactive (high) when the host port is not in use.
I/O
~HostIntrpt
44
Host Interrupt (output). A low assertion on this pin indicates that a host interrupt condition
exists that may require special host action.
I/O
HostData0
50
Host Port Data 0-7 (bi-directional, tri-stated). These signals form the 8 bit host data port used
HostData1
61
during communication to/from the chip set. This port is controlled by ~HostSlct, ~HostWrite,
HostData2
53
~HostRead and HostCmd.
HostData3
65
HostData4
67
HostData5
62
HostData6
64
HostData7
60
I/O
CPData4
18
I/O chip to CP chip data port (bi-directional). These 8 bits are connected to the corresponding
CPData5
5
Data4-11 pins on the CP chip, and facilitate communication to/from the I/O and CP chips..
CPData6
6
CPData7
7
CPData8
8
CPData9
17
CPData10
3
CPData11
1
I/O
Vcc
4, 21, 25, 38, 55 I/O chip supply voltage pin. All of these pins must be connected to the supply voltage. Supply
voltage = 4.75 to 5.25 V
I/O
GND
14, 15, 32, 49, 54, I/O chip ground pin. All of these pins must be connected to the power supply return.
66
14
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