MB90352 Ver la hoja de datos (PDF) - Fujitsu
Número de pieza
componentes Descripción
Fabricante
MB90352 Datasheet PDF : 64 Pages
| |||
MB90350 Series
s PRODUCT LINEUP
Part Number
Parameter
MB90F352/S, MB90352/S*1
MB90V340A-101/102
CPU
F2MC-16LX CPU
System clock
On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (4 MHz osc. PLL × 6)
ROM
Boot-block, Flash memory
128 Kbytes
External
RAM
4 Kbytes
30 Kbytes
Emulator-specific
power supply*2
Yes
Technology
0.35 µm CMOS with regulator for internal power supply +
Flash memory charge pump for programming voltage
0.35 µm CMOS with
regulator for internal
power supply
Operating
voltage range
3.5 V - 5.5 V : at normal operating (not using A/D converter)
4.0 V - 5.5 V : at using A/D converter/Flash programming
4.5 V - 5.5 V : at using external bus
5 V ± 10%
Temperature range −40 °C to +105 °C (125 °C up to 16 MHz machine clock)
Package
LQFP-64
PGA-299
2 channels
3 channels
UART
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
I2C (400 kbit/s)
1 channel
1 channel
A/D
Converter
15 channels
10-bit or 8-bit resolution
Conversion time : Min 3 µs include sample time (per one channel)
16-bit Reload Timer Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = Machine clock frequency)
(4 channels)
Supports External Event Count function
16-bit
I/O Timer
(2 channels)
Signals an interrupt when overflowing
Supports Timer Clear when a match with Output Compare (Channel 0, 4)
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys = Machine clock freq.)
I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1
I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7
16-bit Output
Compare
(4 channels)
Signals an interrupt when 16-bit I/O Timer match output compare registers.
A pair of compare registers can be used to generate an output signal.
16-bit Input Capture Rising edge, falling edge or rising & falling edge sensitive
(6 channels)
Signals an interrupt upon external event
(Continued)
4
Share Link: 