M66281FP Ver la hoja de datos (PDF) - Renesas Electronics

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Fabricante

M66281FP

5120 × 8-Bit × 2 Line Memory

Renesas Electronics 

M66281FP

Function

When write enable input WEB is set to "L", the contents of data inputs D0 to D7 are written into memory only for 1 line

delay data in synchronization with a rising edge of write clock input WCK to perform writing operation. When this is

the case, the write address counter of memory only for 1 line delay data is incremented simultaneously.

When WEB is set to "H", the writing operation is inhibited and the write address counter of memory only for 1 line

delay data stops.

When write reset input WRESB is set to "L", the write address counter of memory only for 1 line delay data is

initialized.

When read enable input REB is set to "L", the contents of memory only for 1 line delay data are output to data outputs

Q00 to Q07 and the contents of memory only for 2 line delay data are output to Q10 to Q17 in synchronization with a

rising edge of read clock input RCK to perform reading operation.

When this is the case, the read address counters of memory only for 1 line delay data and memory only for 2 line delay

data are incremented simultaneously.

In addition, data of Q00 to Q07 is written into memory only for 2 line delay data in synchronization with a rising edge

of RCK. When this is the case, the write address counter of memory only for 2 line delay data is then incremented.

When REB is set to "H", operation for reading data from memory only for 1 line delay and from memory only for 2 line

delay data is inhibited and the read address counter of each memory stops.

Outputs Q00 to Q07 and Q10 to Q17 are placed in a high impedance state. In addition, the write address counter of

memory only for 2 line delay data then stops.

When read reset input RRESB is set to "L", the read address counters of memory only for 1 line delay data as well as

the write address counter and read address counter of memory only for 2 line delay data are then initialized.

REJ03F0254-0200 Rev.2.00 Sep 14, 2007

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