M66281FP Ver la hoja de datos (PDF) - Renesas Electronics

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M66281FP

5120 × 8-Bit × 2 Line Memory

Renesas Electronics 

M66281FP

Variable Length Delay Bit

1 Line (5120 Bits) Delay

Input data can be written at the rising edge of WCK after write cycle and output data is read at the rising edge of RCK

before read cycle to easily make 1 line delay.

WCK

RCK

0 cycle 1 cycle 2 cycle

5120 cycle 5121 cycle 5122 cycle

5118 cycle 5119 cycle (0')

(1')

(2')

tRESS tRESH

WRESB

RRESB

tDS tDH

tDS tDH

Dn

(0)

(1)

(2)

(5117)

(5118)

(5119)

(0')

(1')

(2')

(3')

Q0n

(Q1n)

5120 cycle

tAC

tOH

(0)

(1)

(2)

(3)

WEB, REB = "L"

n-bit Delay Bit

(Reset at cycles according to the delay length)

WCK

RCK

0 cycle 1 cycle 2 cycle

tRESS tRESH

WRESB

RRESB

tDS tDH

n cycle n + 1 cycle n + 2 cycle n + 3 cycle

n − 2 cycle n − 1 cycle (0')

(1')

(2')

(3')

tRESS tRESH

tDS tDH

Dn

(0)

(1)

(2)

(n − 3)

(n − 2)

(n − 1)

(0')

(1')

(2')

(3')

Q0n

(Q1n)

m cycle

tAC

tOH

(0)

(1)

(2)

(3)

WEB, REB = "L"

m≥3

REJ03F0254-0200 Rev.2.00 Sep 14, 2007

Page 11 of 15

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