M5M44260CJ-5 Ver la hoja de datos (PDF) - MITSUBISHI ELECTRIC
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M5M44260CJ-5 Datasheet PDF : 29 Pages
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MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Write Cycle (Early Write and Delayed Write)
Symbol
Parameter
tWC
tRAS
tCAS
tCSH
tRSH
tWCS
tWCH
tCWL
tRWL
tWP
tDS
tDH
tOEH
Write cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Write setup time before CAS low
Write hold time after CAS low
CAS hold time after W low
RAS hold time after W low
Write pulse width
Data setup time before CAS low or W low
Data hold time after CAS low or W low
OE hold time after W low
Limits
M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S Unit
Min Max Min Max Min Max
90
110
130
ns
50 10000 60 10000 70 10000
ns
13 10000 15 10000 20 10000
ns
50
60
70
ns
13
15
20
ns
(Note 23) 0
0
0
ns
8
10
15
ns
13
15
20
ns
13
15
20
ns
8
10
15
ns
0
0
0
ns
8
10
15
ns
13
15
20
ns
Read-Write and Read-Modify-Write Cycles
Limits
Symbol
Parameter
M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S Unit
Min Max Min Max Min Max
tRWC
Read write/read modify write cycle time
(Note 22) 126
150
180
ns
tRAS
RAS low pulse width
tCAS
CAS low pulse width
tCSH
CAS hold time after RAS low
86 10000 100 10000 120 10000
ns
49 10000 55 10000 70 10000
ns
86
100
120
ns
tRSH
RAS hold time after CAS low
49
55
70
ns
tRCS
tCWD
Read setup time before CAS low
Delay time, CAS low to W low
0
0
0
ns
(Note 23) 31
35
45
ns
tRWD
tAWD
tCWL
Delay time, RAS low to W low
Delay time, address to W low
CAS hold time after W low
(Note 23) 68
80
95
ns
(Note 23) 43
50
60
ns
13
15
20
ns
tRWL
RAS hold time after W low
13
15
20
ns
tWP
Write pulse width
tDS
Data setup time before CAS low or W low
8
10
15
ns
0
0
0
ns
tDH
Data hold time after CAS low or W low
tOEH
OE hold time after W low
8
10
15
ns
13
15
20
ns
Note 22: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
23: tWCS, tCWD, tRWD and tAWD and tCPWD are specified as reference points only. If tWCS ≥ tWCS(min) the cycle is an early write cycle and the DQ pins
will remain high impedance throughout the entire cycle. If tCWD ≥ tCWD(min), tRWD ≥ tRWD(min), tAWD ≥ tAWD(min) and tCPWD ≥ tCPWD(min)
(for fast page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address.
If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH) is indeterminate.
6
M5M44260CJ,TP-5,-5S : Under development
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