JLC1562B(2000) Ver la hoja de datos (PDF) - ON Semiconductor
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JLC1562B Datasheet PDF : 8 Pages
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JLC1562B
DC CHARACTERISTICS (Referenced to Vss)
Guaranteed Limit
Symbol
Parameter
Min
Max
VIH
Maximum Input Voltage, “H”
0.7 Vdd
–
VIL
Maximum Input Voltage, “L”
–
VOL
Maximum Output Voltage, “L” (Iout = 4mA)
–
Iin
Maximum Input Leakage Current (Vin = Vdd or Vss, SCL pin only)
–
Ioz
Maximum Output Hi–Z Leakage Current (Output = High Impedance; Vout = Vdd)
–
Cin
Maximum Input Capacitance (Input Pin)
–
Cout Maximum Output Capacitance (Output Pin)
–
0.3 Vdd
0.3
± 1.0
± 5.0
10
15
Ci/o
VICR
Maximum I/O Capacitance (I/O Pin)
Comparator Common Mode Input Voltage Range
–
15
0
Vdd – 1.5
ICC
Maximum Quiescent Supply Current (per Package)
COMPARATOR AC CHARACTERISTICS
–
5.0
Guaranteed Limit
Symbol
Parameter
Test Conditions
Min
Typ
Max
tPD Maximum Propagation Delay
Vref = 1.5V, 10mV overdrive
–
Vref = 1.5V, 100mV overdrive
–
1.0
–
0.2
–
DA COMPARATOR CHARACTERISTICS
Guaranteed Limit
Symbol
Parameter
Min
Typ
Max
DNL
DAC Referential NON–Linearity
±1/4 LSB
eFS
DAC Full Scale Error
eZC
DAC Zero Scale Error
TIMING CHARACTERISTICS
±1 LSB
±1 LSB
Guaranteed Limit
Symbol
Parameter
Min
Max
fCL
SCL CLOCK Frequency
0
100
tBUF
tHD:STA
tLOW
BUS Free Time (Between “STOP” and “START”)
HOLD Time for “START”
HOLD Time at SCL CLOCK LOW
4.7
–
4.0
–
4.7
–
tHIGH
tHD:DAT
HOLD Time at SCL CLOCK HI
DATA HOLD Time
4.0
–
0
–
tSU:DAT
tR
tF
DATA SETUP Time
Rise Time (SDA and SCL)
Fall Time (SDA and SCL)
250
–
–
1000
–
300
tSU:STO SETUP Time for “STOP”
4.0
–
Unit
V
V
V
µA
µA
pF
pF
pF
V
mA
Unit
µS
µS
Unit
Unit
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
SDA
tBUF
SCL
tLOW
tR
tF
tHD:STA
tHD:DAT tHIGH
tSU:DAT
http://onsemi.com
3
tSU:STO
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