ISL3034E Ver la hoja de datos (PDF) - Intersil

Número de pieza

componentes Descripción

Fabricante

ISL3034E

4-Channel And 6-Channel High Speed, Auto-direction Sensing Logic Level Translators

Intersil 

ISL3034E, ISL3035E, ISL3036E

Electrical Specifications

PARAMETER

VCC = +2.2V to +3.6V, VL = +1.35V to +3.2V, EN = VL, unless otherwise noted. Typical values are at

VCC = +3.3V, VL = +1.8V and TA = +25°C. (Note 6). (Continued)

SYMBOL

TEST CONDITIONS

TEMP MIN

MAX

(°C) (Note 8) TYP (Note 8) UNITS

I/OVL, CLK_RET Fall Time

tFVL

RS = 150Ω, CI/OVL = 15pF,

CCLK_RET = 15pF

I/OVCC, CLK_VCC Propagation

Delay (Driving I/OVL, CLK_VL)

tPDVCC

RS = 150Ω, CI/OVCC = 10pF,

CCLK_VCC = 10pF, push-pull

drivers

VL ≥ 1.35V Full

-

VL ≥ 1.62V Full

-

VL ≥ 1.35V Full

-

VL ≥ 1.62V Full

-

-

4

ns

-

3.5

ns

-

7.5

ns

-

6.5

ns

tPDVCC Channel-to-Channel

Skew (Note 9)

tSKEWC

VL ≥ 1.35V Full

VL ≥ 1.62V Full

I/OVL, CLK_RET Propagation

Delay (Driving I/OVCC,

CLK_VCC)

tPDVL RS = 150Ω, CI/OVL = 15pF, CCLK_RET = 15pF,

Full

push-pull drivers

tPDVL Channel-to-Channel Skew tSKEWL

(Note 9)

VL ≥ 1.35V Full

VL ≥ 1.62V Full

Delay from EN High to I/OVCC tEN-VCC RLOAD = 1MΩ, CI/OVCC = 10pF (ISL3034E and

25

Active

ISL3036E)

-

-

1.3

ns

-

-

1

ns

-

-

6.5

ns

-

-

1.3

ns

-

-

0.8

ns

-

1.5

-

µs

Delay from EN High to I/OVL

tEN-VL RLOAD = 1MΩ, CI/OVL = 15pF (ISL3034E and

25

-

1.5

-

µs

Active

ISL3036E)

Maximum Data Rate

D.R.1.35 Push-pull operation,

VL ≥ 1.35V Full

85

-

D.R.1.6

RSOURCE = 150Ω,

CI/OVCC = 10pF, CI/OVL = 15pF,

VL ≥ 1.62V Full

100

-

CCLK_VCC = 10pF,

CCLK_RET = 15pF

-

Mbps

-

Mbps

NOTES:

6. VL must be less than or equal to VCC - 0.2V during normal operation. However, VL can be greater than VCC during start-up and shutdown

conditions and the part will not latch-up nor be damaged.

7. Input thresholds are referenced to the boost circuit.

8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

9. Delta between all I/OVL channel prop delays, or delta between all I/OVCC channel prop delays, all channels tested at the same test conditions.

Test Circuits and Waveforms

VL

EN

VL

VCC

SIGNAL

GENERATOR

I/OVL

150Ω

I/OVCC

CL

I/OVL

50%

tPLH

I/OVCC

50%

10%

tRVCC

90%

VL

50%

90%

0V

tPHL

VOH

50%

10%

VOL

tFVCC

tPDVCC = tPLH or tPHL

FIGURE 1A. TEST CIRCUIT

FIGURE 1B. MEASUREMENT POINTS

FIGURE 1. I/OVCC OUTPUT PROPAGATION DELAY AND TRANSITION TIMES (PUSH - PULL)

6

FN6492.0

March 31, 2009

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