HV7620(2013) Ver la hoja de datos (PDF) - Supertex Inc
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HV7620 Datasheet PDF : 7 Pages
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HV7620
DC Electrical Characteristics
(Over operating supply voltages and temperature, unless otherwise noted, VDD1 = 5.0V, VDD2 = 12V, VPP = 200V and Tj = 25°C)
Sym Parameter
Min Max Units Conditions
IDD1
VDD1 supply current
-
5.0
mA fCLK = 10MHz
IDD2
VDD2 supply current
-
20
mA VDD2 = 13.2V, fCLK = 10MHz
IPP
High voltage supply current
-
2.0
mA All outputs high or low
IDD1Q
Quiescent VDD1 supply current
-
100
µA All input = VDD1
IDD2Q
Quiescent VDD2 supply current
-
100
µA All input = VDD1
VOH
High-level output
HVOUT
185
-
Data OUT VDD -1
-
V
IO = -50mA
IO = -100µA
VOL
Low-level output
HVOUT
-
20
V
IO = +50mA
Data OUT
-
1.0
IO = +100µA
IIH
High-level logic input current
-
1.0
µA
VIN = VDD1
IIL
Low-level logic input current
-
-10
µA VIN = 0V
VGG HVGND to LVGND voltage difference
-1.0
1.0
V ---
AC Electrical Characteristics
(Logic signal inputs and data inputs have tr, tf ≤ 5ns. VDD1 = 5.0V or 12V, VDD2 = 12V, VPP = 200V and Tj = 25°C)
Sym Parameter
Min Max Units Conditions
fCLK
Clock frequency
VDD1 = 5.0V
-
VDD1 = 12V
-
tWL, tWH Clock width high or low
40
tSU
Data set-up time before clock rises
20
tH
Data hold time after clock rises
20
tON, tOFF Time from latch enable to HVOUT
-
tWLE
LE pulse width
25
tDLE
Delay time clock to LE low to high
50
tSLE
LE set-up time before clock rises
20
tDLF, tDLN BL or CS low to high to HVOUT
-
tCOF, tCON Clock to HVOUT
-
tDLH
Delay time clock to data low
to high
VDD1 = 5.0V
VDD1 = 12V
-
-
tDHL
Delay time clock to data high
to low
VDD1 = 5.0V
VDD1 = 12V
-
-
10
5.0
MHz Per register, CL = 15pF
-
ns ---
-
ns ---
-
ns ---
275
ns CL = 15pF
-
ns ---
-
ns ---
-
ns ---
250
ns ---
275
ns ---
250
100
ns CL = 15pF
250
100
ns CL = 15pF
Doc.# DSFP-HV7620
C112213
Supertex inc.
3
www.supertex.com
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