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Fabricante

NJM2211D

FSK DEMODULATOR / TONE DECODER

Japan Radio Corporation  

NJM2211

Design Example

75 Band FSK demodulator with mark / space frequencies of 1110 / 1170Hz :

Step 1 : Calculate f0 :

f0=(1110+1170) (1 / 2)=1140Hz

Step 2 : Choose R0=20kΩ (18kΩ fixed resistor in series with 5kΩ potentiometer)

Step 3 : Calculate C0 from VCO Frequency vs. Timing Capacitor : C0 =0.044µF

Step 4 : Calculate R1 : R1=R0 (1140 / 60) =380kΩ

Step 5 : Calculate C1 : C1=C0 / 4=0.011µF

Note : All values except R0 can be rounded off to nearest standard value.

FSK Decoding With Carrier Detect

The lock-detect section of the NJM2211 can be used as a carrier detect option for FSK decoding. The recommended

circuit connection for this application is shown in Figure 3. The open-collector lock-detect output, pin 6, is shorted to the

data output (pin 7). Thus, the data output will be disabled at "low" state, until there is a carrier within the detection band of

the PLL, and the pin 6 output goes "high" to enable the data output.

The Minimum value of the lock-detect filter capacitance CD is inversely proportional to the capture range, ±∆fc. This is

the range of incoming frequencies over which the loop can acquire lock and is always less than the tracking range. It is

further limited by C1. For most applications, ∆fc<∆f / 2, For RD=470kΩ, the approximate minimum value of CD can be

determined by :

CD (µF) ≥ 16 / capture range in Hz

With values of CD that are too small, chatter can be observed on the lock-detect output as an incoming signal

frequency approaches the capture bandwidth. Excessively large values of CD will slow the response time of the

lock-detect output.

Tone Detection

Figure 4 shows the generalized circuit connection for tone detection. The logic outputs, Q and Q at pins 5 and 6 are

normally at "high" and "low" logic states, respectively. When a tone is present within the detection band of the PLL, the

logic state at these outputs becomes reversed for the duration of the input tone. Each logic output can sink 5mA of load

current.

Both logic outputs at pins 5 and 6 are open-collector type stages, and require external pull-up resistors RL1 and RL2 as

shown in Figure 4.

With reference to Figure 1 and 4, the function of the external circuit components can be explained as follows : R0 and

C0 set VCO center frequency, R1 sets the detection bandwidth, C1 sets the lowpass-loop filter time constant and the

loop damping factor, and RL1 and RL2 are the respective pull-up resistors for the Q and Q logic outputs.

Figure 3. FSK Demodulation with Carrier Detect Capability

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Figure 4. Tone Detection

Ver.2003-12-09

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