HEF4013BT(2015) Ver la hoja de datos (PDF) - NXP Semiconductors.

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HEF4013BT
(Rev.:2015)

Dual D-type flip-flop

NXP Semiconductors. 

Nexperia

HEF4013B

Dual D-type flip-flop

Table 7. Dynamic characteristics …continued

Tamb = 25 C; unless otherwise specified. For test circuit see Figure 6.

Symbol Parameter

Conditions

VDD

Extrapolation formula Min Typ Max Unit

trec

recovery time

nSD input;

see Figure 5

5V

10 V

+15 5

15 0

- ns

- ns

15 V

15

0

- ns

nCD input;

see Figure 5

5V

10 V

40 25 - ns

25 10 - ns

15 V

25 10 - ns

fclk(max) maximum clock

frequency

see Figure 4

5V

10 V

7 14 - MHz

14 28 - MHz

15 V

20 40 - MHz

[1] Typical values of the propagation delays and output transition times can be calculated with the extrapolation formulas. CL is given in pF.

Table 8. Dynamic power dissipation

VSS = 0 V; tr = tf  20 ns; Tamb = 25 C.

Symbol Parameter

VDD Typical formula

Where

PD

dynamic power dissipation 5 V PD = 850  fi + (fo  CL)  VDD2 W fi = input frequency in MHz;

10 V PD = 3600  fi + (fo  CL)  VDD2 W fo = output frequency in MHz;

15 V PD = 9000  fi + (fo  CL)  VDD2 W CL = output load capacitance in pF;

(fo  CL) = sum of the outputs;

VDD = supply voltage in V.

HEF4013B

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 9 — 10 December 2015

© Nexperia B.V. 2017. All rights reserved

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