GTLP6C816 Ver la hoja de datos (PDF) - Fairchild Semiconductor

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GTLP6C816

GTLP-to-TTL 1:6 Clock Driver

Fairchild Semiconductor 

Test Circuit and Timing Waveforms

Test Circuit for A Outputs

Test Circuit for B Outputs

Note A: CL includes probes and jig capacitance.

Note B: For B-Port CL = 30 pF is used for worst case.

Note A: CL includes probes and jig capacitance.

Voltage Waveforms Enable and Disable Times A-Port

Voltage Waveforms Propagation Delay (Vm = VCC/2 for A-Port and 1.0 for B-Port)

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