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AT17LV256A

FPGA Configuration EEPROM Memory

Atmel Corporation 

Pin Configurations

20 PLCC

Pin

2

4

8

Name

DATA

DCLK

OE

WP

9

nCS

10

GND

12

nCASC

A2

18

SER_EN

20

VCC

I/O Description

I/O Three-state DATA output for configuration. Open-collector bi-directional pin for programming.

I Clock input. Used to increment the internal address and bit counter for reading and programming.

I Output enable (active High) and reset (active Low) when SER_EN is High. A Low logic level resets

the address counter. A High logic level (with nCS Low) enables DATA and permits the address

counter to count. The logic polarity of OE is programmable and must be set active High (RESET

active Low) by the user during programming for Altera applications.

I Write Protect (WP) input (when nCS is Low) during programming only (i.e., when SER_EN is Low).

When WP is Low, the entire memory can be written. When WP is enabled (High), the lowest block of

the memory cannot be written. This function is not available during FPGA loading operations. Please

refer to the “Programming Specification for Atmel’s Configuration EEPROM” application note for

more details.

I Chip select input (active Low). A Low input (with OE active) allows DCLK to increment the address

counter and enables DATA to drive out. A High level on nCS disables both the address and bit

counters and forces the device into a low-power standby mode. Note that this pin will not

enable/disable the device in the 2-wire Serial Programming Mode (i.e., when SER_EN is Low).

Ground pin. A 0.2 µF decoupling capacitor should be placed between the VCC and GND pins.

O Cascade select output (active Low). This output goes Low when the address counter has reached its

maximum value. In a daisy-chain of AT17A Series devices, the nCASC pin of one device must be

connected to the nCS input pin of the next device in the chain. It will stay Low as long as nCS is Low

and OE is High. It will then follow nCS until OE goes Low, thereafter, nCASC will stay High until the

entire EEPROM is read again.

I Device selection input, A2. This is used to enable (or select) the device during programming (i.e.,

when SER_EN is Low; please refer to the “Programming Specification for Atmel’s Configuration

EEPROM” application note for more details).

I Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low enables

the 2-wire Serial Programming Mode.

+3.3V/+5V Power Supply Pin.

6 AT17C/LV65A/128A/256A

0996D–08/01

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