AT17LV256A Ver la hoja de datos (PDF) - Atmel Corporation
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AT17LV256A Datasheet PDF : 15 Pages
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AT17C/LV65A/128A/256A
Figure 3. FPGA Device Configured with Multiple AT17A Series Configurators(1)(2)(3)
VCC
VCC VCC
VCC
1 kW
0.1 mF
GND
1 kW
EPF10K
nCONFIG DCLK
DATA0
CONF_DONE
nSTATUS
nS/P
MSEL0
MSEL1
GND
AT17C65(A)/128(A)/256(A)
1 kW AT17LV65(A)/128(A)/256(A)
Device 1
DCLK
DATA
SER_EN
nCS
nCASC
OE
READY
AT17C65(A)/128(A)/256(A)
AT17LV65(A)/128(A)/256(A)
Device 2
VCC
DCLK
DATA
nCS
SER_EN
OE
Notes:
1. Reset polarity must be set active Low.
2. RC filter recommended for input to nCONFIG to delay configuration until VCC is stable. (nCONFIG can instead be connected
to an active Low system reset signal.)
3. The use of the READY pin is optional.
AT17A Series Reset
Polarity
The AT17 Series Configurator allows the user to program the polarity of the OE pin as
either RESET/OE or RESET/OE. This feature is supported by industry-standard pro-
grammer algorithms. For more details on programming the EEPROM’s reset polarity,
please reference the “Programming Specification for Atmel’s FPGA Configuration
EEPROMs” application note.
Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can
be programmed by the 2-wire serial bus. The programming is done at VCC supply only.
Programming super voltages are generated inside the chip. See the “Programming
Specification for Atmel’s Configuration EEPROM” application note for further informa-
tion. The AT17CXXXA parts are read/write at 5V nominal. The AT17LVXXXA parts are
read/write at 3.3V nominal.
Standby Mode
The AT17C/LV65A/128A/256A enters a low-power standby mode whenever nCS is
asserted High. In this mode, the configurator consumes less than 75 µA of current
at 5.0V. The output remains in a high-impedance state regardless of the state of the OE
input.
5
0996D–08/01
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