AT17LV256A Ver la hoja de datos (PDF) - Atmel Corporation

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componentes Descripción

Fabricante

AT17LV256A

FPGA Configuration EEPROM Memory

Atmel Corporation 

Figure 1. FPGA Device Configured with a Single AT17A Series Configurator(1)(2)(3)

VCC

VCC

VCC

EXT_CLK

1 kW

0.1 mF

GND

EPF6K

nCONFIG

DCLK

DATA0

CONF_DONE

nSTATUS

nS/P

MSEL0

1 kW

1 kW

AT17C65(A)/128(A)/256(A) VCC

AT17LV65(A)/128(A)/256(A)

DCLK

DATA

nCS

SER_EN

OE

READY

GND

Notes:

1. Reset polarity must be set active Low.

2. RC filter recommended for input to nCONFIG to delay configuration until VCC is stable. (nCONFIG can instead be connected

to an active Low system reset signal.)

3. The use of the READY pin is optional.

Figure 2. FPGA Device Configured with a Single AT17A Series Configurator(1)(2)(3)

VCC VCC VCC

VCC

EPF8K

nCONFIG

DCLK

DATA0

CONF_DONE

nSTATUS

nS/P

MSEL0

MSEL1

GND

1 k9 1 k9

AT17C65(A)/128(A)/256(A)

AT17LV65(A)/128(A)/256(A) VCC

DCLK

DATA

nCS

OE

SER_EN

READY

Notes:

1. Reset polarity must be set active Low.

2. RC filter recommended for input to nCONFIG to delay configuration until VCC is stable. (nCONFIG can instead be connected

to an active Low system reset signal.)

3. The use of the READY pin is optional.

4 AT17C/LV65A/128A/256A

0996D–08/01

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