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AT17LV256A-10JC

FPGA Configuration EEPROM Memory

Atmel Corporation 

Block Diagram

POWER ON

RESET

Device Configuration

The control signals for the configuration EEPROM – nCS, OE, and DCLK – interface

directly with the FPGA device control signals. All FPGA devices can control the entire

configuration process and retrieve data from the configuration EEPROM without requir-

ing an external intelligent controller.

The configuration EEPROM device’s OE and nCS pins together control the tri-state

buffer on the DATA output pin and enable the address counter. When OE is driven Low,

the configuration EEPROM resets its address counter and tri-states its DATA pin. The

nCS pin also controls the output of the AT17A Series Configurator. If nCS is held High

after the OE reset pulse, the counter is disabled and the DATA output pin is tri-stated.

When nCS is subsequently driven Low, the counter and the DATA output pin are

enabled. When OE is driven Low again, the address counter is reset and the DATA out-

put pin is tri-stated, regardless of the state of nCS.

When the configurator has driven out all of its data and nCASC is driven Low, the device

tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the

address counter is automatically reset.

2 AT17C/LV65A/128A/256A

0996D–08/01

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