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QL6325-E

FPGA Combining Performance, Density, and Embedded RAM

QuickLogic Corporation 

QL6325E Eclipse-E Data Sheet Rev. F

Figure 4: Cascaded RAM Modules

WDATA

WADDR

RAM

Module

(2,304 bits)

RDATA

RADDR

WDATA

RAM

Module

(2,304 bits)

RDATA

The RAM modules are dual-port, with completely independent READ and WRITE ports and separate READ

and WRITE clocks. The READ ports support asynchronous and synchronous operation, while the WRITE

ports support synchronous operation. Each port has 18 data lines and 8 address lines, allowing word lengths

of up to 18 bits and address spaces of up to 256 words. Depending on the mode selected, however, some

higher order data or address lines may not be used.

The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read Enable (RE) acts

as a clock enable for synchronous READ operation (ASYNCRD input low), or as a flow-through enable for

asynchronous READ operation (ASYNCRD input high).

Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by

connecting corresponding address lines together and dividing the words between modules.

A similar technique can be used to create depths greater than 256 words. In this case address signals higher

than the MSB are encoded onto the write enable (WE) input for WRITE operations. The READ data outputs

are multiplexed together using encoded higher READ address bits for the multiplexer SELECT signals.

The RAM blocks can be loaded with data generated internally (typically for RAM or FIFO functions) or with

data from an external PROM (typically for ROM functions).

Embedded Computational Unit (ECU)

Traditional Programmable Logic architectures do not implement arithmetic functions efficiently or effectively—

these functions require high logic cell usage while garnering only moderate performance results.

The Eclipse-E architecture allows for functionality above and beyond that achievable using programmable logic

devices. By embedding a dynamically reconfigurable computational unit, the Eclipse-E device can address

various arithmetic functions efficiently. This approach offers greater performance and utilization than

traditional programmable logic implementations. The embedded block is implemented at the transistor level

as shown in Figure 5.

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