QL6325-E Ver la hoja de datos (PDF) - QuickLogic Corporation

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QL6325-E

FPGA Combining Performance, Density, and Embedded RAM

QuickLogic Corporation 

QL6325E Eclipse-E Data Sheet Rev. F

the I/O pin through a multiplexer. The multiplexer allows either a combinatorial or a registered signal to be

driven to the I/O pin. The addition of an output register will also decrease the Tco. Since the output register

does not need to drive the routing the length of the output path is also reduced.

The three-state output buffer controls the flow of data from the array logic to the I/O pin and allows the I/O

pin to act as an input and/or output. The buffer's output enable can be individually controlled by the logic cell

array or any pin (through the regular routing resources), or it can be bank-controlled through one of the global

networks. The signal can also be either combinatorial or registered. This is identical to that of the flow for the

output cell. For combinatorial control operation data is routed from the logic array through a multiplexer to

the three-state control. The IOCTRL pins can directly drive the OE and CLK signals for all I/O cells within the

same bank.

For registered control operation, the array logic drives the D input of the OE cell register which in turn drives

the three-state control through a multiplexer. The multiplexer allows either a combinatorial or a registered

signal to be driven to the three-state control.

When I/O pins are unused, the OE controls can be permanently disabled, allowing the output cell register to

be used for registered feedback into the logic array.

I/O cell registers are controlled by clock, clock enable, and reset signals, which can come from the regular

routing resources, from one of the global networks, or from two IOCTRL input pins per bank of I/O's. The

CLK and RESET signals share common lines, while the clock enables for each register can be independently

controlled. I/O interface support is programmable on a per bank basis. The two Eclipse-E devices contain eight

I/O banks. Figure 8 illustrates the I/O bank configurations.

Each I/O bank is independent of other I/O banks and each I/O bank has its own VCCIO and INREF supply

inputs. A mixture of different I/O standards can be used on the device; however, there is a limitation as to

which I/O standards can be supported within a given bank. Only standards that share a common VCCIO and

INREF can be shared within the same bank (e.g., PCI and LVTTL).

VCCIO(F)

Figure 8: Multiple I/O Banks

INREF(F)

VCCIO(E)

INREF(E)

VCCIO(G)

PLL

INREF(G)

VCCIO(H)

INREF(H)

PLL

Embedded RAM Blocks

Embeded Computational Units

Fabric

Embedded RAM Blocks

PLL

VCCIO(D)

INREF(D)

PLL

VCCIO(C)

INREF (C)

VCCIO(A)

INREF(A)

VCCIO(B)

INREF(B)

10

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