HSP50216(2000) Ver la hoja de datos (PDF) - Intersil
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HSP50216 Datasheet PDF : 53 Pages
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HSP50216
Pin Descriptions (Continued)
NAME
TYPE
DESCRIPTION
SYNCB
O
Serial Data Output 1B sync signal. This signal is used to indicate the start of a data word and/or frame of
data. The polarity and position of SYNCB is programmable.
SYNCC
O
Serial Data Output 1C sync signal. This signal is used to indicate the start of a data word and/or frame of
data. The polarity and position of SYNCC is programmable.
SYNCD
O
Serial Data Output 1D sync signal. This signal is used to indicate the start of a data word and/or frame of
data. The polarity and position of SYNCD is programmable.
MICROPROCESSOR INTERFACE
P(15:0)
I/O
Microprocessor Interface Data bus. See Microprocessor Interface Section. P15 is the MSB.
ADD(2:0)
I
Microprocessor Interface Address bus. ADD2 is the MSB. See Microprocessor Interface Section. Note:
ADD2 is not used but designated for future expansion.
WR
I
Microprocessor Interface Write Signal. The data on P(15:0) is written to the destination selected by
ADD(2:0) on the rising edge of WR when CE is asserted (low). See Microprocessor Interface Section.
RD
I
Microprocessor Interface Read Strobe. The data at the address selected by ADD(2:0) is placed on
P(15:0) when RD is asserted (low) and CE is asserted (low). See Microprocessor Interface Section.
µP MODE
I
Microprocessor Interface Mode Control. This pin is used to select the Read/Write mode for the
Microprocessor Interface.
CE
I
Microprocessor Interface Chip Select. Active low. This pin has the same timing as the address pins.
INTRPT
O
Microprocessor Interrupt Signal. Asserted for a programmable number of clock cycles when new data is
available on the selected Channel.
Functional Description
The HSP50216 is a four channel digital receiver integrated
circuit offering exceptional dynamic range and flexibility.
Each of the four channels consists of a front-end NCO/digital
mixer/CIC-filter block and a back-end FIR/AGC/polar-
conversion block. The parameters for the four channels are
independently programmable. Four parallel data input
busses (A(15:0), B(15:0), C(15:0) and D(15:0)) and four
serial data outputs (SDxA, SDxB, SDxC, and SDxD; x = 1 or
2) are provided. Each input can be connected to any or all of
the internal signal processing channels, Channels 0, 1, 2
and 3. The output of each channel can be routed to any of
the serial outputs. Outputs from more than one channel can
be multiplexed through a common output if the channels are
synchronized. The four channels share a common input
clock and a common serial output clock, but the output
sample rates can be synchronous or asynchronous. Bus
multiplexers between the front end and back end sections
provide flexible routing between channels for cascading
back-end filters or for routing one front end to multiple back
ends for polyphase filtering (to provide wider bandwidth
filtering). A level detector is provided to monitor the signal
level on any of the parallel data input busses.
Each front end NCO/digital mixer/CIC filter section includes
a quadrature numerically controlled oscillator (NCO), digital
mixer, and a cascaded-integrator-comb filter (CIC). The
NCO has a 32-bit frequency control word for 16.3MHz tuning
resolution at an input sample rate of 70MSPS. The SFDR of
the NCO is >115dB. The CIC filter order is programmable
between 1 and 5 and the CIC decimation factor can be
programmed from 4 to 65536, depending on the number of
stages selected.
Each back end section includes an FIR processing block, an
AGC and a cartesian-to-polar coordinate converter. The FIR
processing block is a flexible filter compute engine that can
compute a single FIR or a set of filters. A single filter in a
chain can have up to 256 taps and the total number of taps
in a set of filters can be up to 384. The filter compute engine
supports a variety of filter types including decimation,
interpolation and resampling filters. The coefficients for the
programmable digital filters are 22 bits wide. Coefficients are
provided in ROM for several halfband filter responses and for
a resampler. The AGC section can provide up to 96dB of
either fixed or automatic gain control. For automatic gain
control, two settling modes and two sets of loop gains are
provided. Separate attack and decay slew rates are provided
for each loop gain. Programmable limits allow the user to
select a gain range less than 96dB. The outputs of the
cartesian-to-polar coordinate conversion block, used by the
AGC loop, are also provided as outputs to the user for
demodulation.
The HSP50216 supports both fixed and floating point
parallel data input modes. The floating point modes support
gain ranging A/D converters. Gated, interpolated and
multiplexed data input modes are supported. The serial data
output word width for each data type can be programmed to
one of ten output bit widths from 4-bit fixed point through 32-
bit IEEE floating point.
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