GM72V66841ELT Ver la hoja de datos (PDF) - Hynix Semiconductor
Número de pieza
componentes Descripción
Fabricante
GM72V66841ELT Datasheet PDF : 10 Pages
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GM72V66841ET/ELT
Relationship Between Frequency and Minimum Latency
Parameter
-7
-75
-8
-7K
-7J
frequency(MHz)
Symbol 143 100 133 100 125 100 100 100 100 66 Notes
tCK (ns)
Active command to column
command (same bank)
lRCD
Active command to active
command (same bank)
lRC
Active command to Precharge
command (same bank)
lRAS
Precharge command to active
command (same bank)
lRP
Write recovery or last data-in to
Precharge command (same bank)
lRWL
Active command to active
command (different bank)
lRRD
Self refresh exit time
lSREX
Last data in to active command
(Auto Precharge, same bank)
lAPW
Self refresh exit to command
input
lSEC
Precharge
(CL=2)
lHZP
command to
high impedance
(CL=3)
lHZP
Last data out to active
command
lAPR
(auto Precharge) (same bank)
Last data out to
(CL=2)
lEP
Precharge
(early Precharge) (CL=3)
lEP
Column command to column
command
lCCD
Write command to data in
latency
lWCD
DQM to data in
lDID
7 10 7.5 10 8 10 10 10 10 15
323232 2222
1
9
79
7
9
7
7
77
6
= l[ RAS
+lRP], 1
656565 5554 1
323232 2222
1
111111 1111
1
222222 2222
1
111112 1112
4
34
3
4
3
3
33
3
= l[ RWL
+lRP], 1
9 7 9 7 9 7 7 7 7 6 = [lRC]
- 2- 2 - 2 22- 2
333333 3333
111111 1111
- -1 - -1 - -1 - 1 - 1 - -1
-2 -2 -2 -2 -2 -2 - 2 - 2 - 2 - 2
111111 1111
000000 0000
000000 0000
DQM to data out
lDOD
222222 2222
CKE to CLK disable
lCLE
111111 1111
Register set to active command lRSA 1 1 1 1 1 1 1 1 1 1
CS to command disable
lCDD
000000 0000
Power down exit to command
input
lPEC
111111 1111
Rev. 1.1/Apr.01
-8-
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