HDMP-1512 Ver la hoja de datos (PDF) - HP => Agilent Technologies

Número de pieza

componentes Descripción

Fabricante

HDMP-1512

Fibre Channel Transmitter and Receiver Chipset

HP => Agilent Technologies 

capacitor on pin LZTC (# 27) will

begin to discharge. After

approximately 2 msec, the

voltage on LZTC falls to the fault

value and the error detector will

bring the FAULT pin (# 29) high

to alert the system. The error

detector will also hold the voltage

on LZMDF low, until a reset is

initiated.

The -LZON pin is used to disable

the laser driver under system

control or in conjunction with an

external open-fiber control (OFC)

chip. This pin is also used to

reset the error detector and

recharge the capacitor on pin

LZTC.

The LZPWRON pin, # 36, is used

to hold off dc power to the laser

driver until proper dc bias is

applied to the laser diode. When

LZPWRON goes high, the laser

driver is enabled, when it is low,

it is disabled. If not used, this pin

should be tied low.

Receiver Operation

The block diagram of the HDMP-

1514 receiver is shown in Figure

5. The functions included on the

receiver are a coaxial cable

equalizer, two independent loss

of light (LOL) detectors, an input

select function, monolithic phase

locked loop and clock recovery

circuits, a clock generator, frame

demultiplexer and comma

detector, power supply super-

visor, and output latch with TTL

drivers. Figures 20 and 21 show

schematically how to terminate

each pin on the HDMP-1514

when used in systems incorporat-

ing either copper or fiber media.

In the most basic sense, the

receiver accepts a serial electrical

data stream at 1062.5 Mbaud or

531.25 Mbaud and recovers the

8B/10B encoded parallel data and

clock that was applied to the

transmitter. Like the transmitter,

the receiver has several configu-

ration options which interrelate

according to the desired mode of

operation.

The two main modes of operation

for the receiver are based on the

desired signalling rate. The

signalling rate is controlled by

the proper setting of the SPDSEL

pin # 71. When this pin is set

low, the receiver operates at a

serial rate of 531.25 Mbaud.

When pin # 71 is set high, the

receiver operates at a serial rate

of 1062.5 Mbaud.

In a typical configuration, the

serial electrical data stream will

be applied to the ± DI pins, # 19

and # 20 on the receiver. The

serial electrical data stream may

have been transmitted over a

fiber optic link or a copper cable

link (several variations of each

link type is possible). For use

with copper links, a selectable

cable equalizer is available at the

input. This equalizer can be

switched into or out of the data

DR_REF

LOL

DETECTORS

± DI

-EQEN

± LIN

CABLE

EQUALIZER

INPUT

SELECT

VCC_HS

SUPPLY

SUPERVISOR

PLL AND

CLOCK

SELECT

INTERNAL

CLOCKS

CLOCK

GENERATOR

RBC0

RBC1

COM_DET

FRAME

DEMUX

AND

COMMA

DETECT

OUTPUT

10

LATCH AND

20

TTL

INTERFACE

10

DATA BYTE 0

Rx [00:09]

DATA BYTE 1

Rx [10:19]

Figure 5. HDMP-1514 (Receiver) Block Diagram.

660

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