HDMP-1514 Ver la hoja de datos (PDF) - HP => Agilent Technologies

Número de pieza

componentes Descripción

Fabricante

HDMP-1514

Fibre Channel Transmitter and Receiver Chipset

HP => Agilent Technologies 

CLOCK

ENCODED DATA

Tx

SERIAL LINK

Rx

ENCODED DATA

Rx

SERIAL LINK

Tx

CLOCK

REF CLOCK

Figure 1. Point-to-Point Data Link.

REF CLOCK

CLOCK

ENCODED DATA

ENCODED DATA

CLOCK

DATA BYTE 0 10

Tx [00:09]

DATA BYTE 1

TTL INTERFACE

AND

INPUT LATCH

20

FRAME

MULTIPLEXER

Tx [10:19] 10

I/O

SELECT

2

± LOUT

CABLE

DRIVERS

2

± SO

TBC

PLL/CLOCK

GENERATOR

INTERNAL

CLOCKS

LASER

DRIVER

2

± LZOUT

LASER

CONTROLS

Figure 2. HDMP-1512 (Tx) Block Diagram.

Transmitter Operation

The block diagram of the HDMP-

1512 transmitter is shown in

Figure 2. The basic functions of

the transmitter chip are the TTL

Interface and Input Latch, Frame

Multiplexing, Input/Output

selection, cable drivers, Laser

Driver, and monolithic Phase

Locked loop clock generator. The

actual operation of each function

changes slightly, according to the

desired configuration and option

settings. Figures 18 and 19 show

schematically how to terminate

each pin on the HDMP-1512

when used in systems incorporat-

ing either copper or fiber media.

There are two main modes of

operation for the transmitter

chip, both are based on the

selected baud rate. The baud rate

is controlled by the appropriate

setting of the SPDSEL pin, #67.

When this pin is set low, the

transmitter operates at a serial

rate of 531.25 Mbaud. When pin

#67 is set high the transmitter

operates at a serial rate of 1062.5

Mbaud. As such, the two main

modes of operation are the

531.25 Mbaud mode and the

1062.5 Mbaud mode.

The transmitter does not encode

the applied data. It assumes the

data is pre-encoded using the

8B/10B encoding scheme as

defined in ANSI X3.230-1994.

The TTL input interface receives

data at the standard TTL levels

specified in the dc Electrical

Specification table. The internal

phase locked loop (PLL) locks to

the transmit byte clock, TBC.

TBC is supplied to the transmitter

chip by the sending system. TBC

should be a 53.125 MHz clock

(± 100 ppm) as defined in

X3.230-1994. Once the PLL has

locked to TBC, all the clocks used

by the transmitter are generated

by the internal clock generator.

657

Share Link: