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HDMP-1546

Fibre Channel Transceiver Chip

HP => Agilent Technologies 

converted back into 10-bit

parallel data, recognizing the

8B/10B comma character to

establish byte alignment.

The recovered parallel data is

presented to the user at TTL

compatible outputs. The receiver

section also recovers two

53.125 MHz receiver byte clocks

that are 180 degrees out of phase

with each other. The parallel data

is properly aligned with the rising

edge of alternating clocks.

The transceiver provides for on-

chip local loop-back functionality,

controlled through an external

input pin. Additionally, the byte

synchronization feature may be

disabled. This may be useful in

proprietary applications which

use alternative methods to align

the parallel data.

HDMP-1536/46 Block

Diagram

The HDMP-1536/46 was designed

to transmit and receive 10-bit

wide parallel data over a single

high-speed line, as specified for

the FC-0 layer of the Fibre

Channel standard. The parallel

data applied to the transmitter is

expected to be encoded per the

Fibre Channel specification,

which uses an 8B/10B encoding

scheme with special reserve

characters for link management

purposes. In order to accomplish

this task, the HDMP-1536/46

incorporates the following:

• TTL Parallel I/Os

• High Speed Phase Lock Loops

• Clock Generation/Recovery

Circuitry

• Parallel to Serial Converter

• High-Speed Serial Clock and

Data Recovery Circuitry

• Comma Character Recognition

Circuitry

• Byte Alignment Circuitry

• Serial to Parallel Converter

INPUT LATCH

The transmitter accepts 10-bit

wide TTL parallel data at inputs

TX[0..9]. The user-provided

reference clock signal, REFCLK,

is also used as the transmit byte

clock. The TX[0..9] and REFCLK

signals must be properly aligned,

as shown in Figure 3.

TX PLL/CLOCK GENERATOR

The transmitter Phase Lock Loop

and Clock Generator (TX PLL/

CLOCK GENERATOR) block is

responsible for generating all

internal clocks needed by the

transmitter section to perform its

functions. These clocks are based

on the supplied reference byte

clock (REFCLK). REFCLK is used

as both the frequency reference

clock for the PLL and the trans-

mit byte clock for the incoming

data latches. It is expected to be

106.25 MHz and properly aligned

to the incoming parallel data (see

Figure 3). This clock is multiplied

by 10 to generate the 1062.5

MHz clock necessary for the high

speed serial outputs.

FRAME MUX

The FRAME MUX accepts the 10-

bit wide parallel data from the

INPUT LATCH. Using internally

generated high speed clocks, this

parallel data is multiplexed into

the 1062.5 MBd serial data

stream. The data bits are trans-

mitted sequentially, from the

least significant bit (TX[0]) to the

most significant bit (TX[9]).

OUTPUT SELECT

The OUTPUT SELECT block

provides for an optional internal

loopback of the high speed serial

signal, for testing purposes.

In normal operation, LOOPEN is

set low and the serial data stream

is placed at ± DOUT. When wrap-

mode is activated by setting

LOOPEN high, the ± DOUT pins

are held static and the serial

output signal is internally

wrapped to the INPUT SELECT

box of the receiver section.

INPUT SELECT

The INPUT SELECT block deter-

mines whether the signal at ± DIN

or the internal loop-back serial

signal is used. In normal opera-

tion, LOOPEN is set low and the

serial data is accepted at ± DIN.

When LOOPEN is set high, the

high-speed serial signal is

internally looped-back from the

transmitter section to the receiver

section. This feature allows for

loop-back testing exclusive of the

transmission medium.

RX PLL/CLOCK RECOVERY

The RX PLL/CLOCK RECOVERY

block is responsible for frequency

and phase locking onto the

incoming serial data stream and

recovering the bit and byte

clocks. An automatic locking

feature allows the Rx PLL to lock

onto the input data stream

without external controls. It does

this by continually frequency

locking onto the 106.25 MHz

clock, and then phase locking

onto the input data stream. An

internal signal detection circuit

monitors the presence of the

input, and invokes the phase

detection as the data stream

appears. Once bit locked, the

receiver generates the high speed

sampling clock at 1062.5 MHz

for the input sampler, and

recovers the two 53.125 MHz

receiver byte clocks (RBC1/

RBC0). These clocks are 180° out

of phase with each other, and are

698

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