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HDMP-1546

Fibre Channel Transceiver Chip

HP => Agilent Technologies 

Fibre Channel Transceiver Chip

Technical Data

HDMP-1536 Transceiver

HDMP-1546 Transceiver

Features

• ANSI X3.230-1994 Fibre

Channel Compatible (FC-0)

• Supports Full Speed

(1062.5 MBd) Fibre Channel

• Compatible with “Fibre

Channel 10-Bit Interface”

Specification

• Low Power Consumption,

630 mW

• Transmitter and Receiver

Functions Incorporated onto

a Single IC

• Auto Frequency Lock

• Small Package Profile

HDMP-1536, 10x10 mm QFP

HDMP-1546, 14x14 mm QFP

• 10-Bit Wide Parallel TTL

Compatible I/Os

• Single +3.3 V Power Supply

Applications

• 1062.5 MBd Fibre Channel

Interface

• FC Interface for Disk Drives

and Arrays

• Mass Storage System I/O

Channel

• Work Station/Server I/O

Channel

• High Speed Proprietary

Interface

• High Speed Backplane

Interface

Description

The HDMP-1536/46 transceiver

is a single silicon bipolar

integrated circuit packaged in a

plastic QFP package. It provides

a low-cost, low-power physical

layer solution for 1062.5 MBd

Fibre Channel or proprietary link

interfaces. It provides complete

FC-0 functionality for copper

transmission, incorporating both

the Fibre Channel FC-0 transmit

and receive functions into a

single device.

This chip is used to build a high-

speed interface (as shown in

Figure 1) while minimizing board

space, power, and cost. It is

compatible with both the ANSI

X3.230-1994/AM 1 - 1996

document and the “Fibre Channel

10-bit Interface” specification.

The transmitter section accepts

10-bit wide parallel TTL data and

multiplexes this data into a high-

speed serial data stream. The

parallel data is expected to be

8B/10B encoded data, or

equivalent. This parallel data is

latched into the input register of

the transmitter section on the

rising edge of the 106.25 MHz

reference clock (used as the

transmit byte clock).

The transmitter section’s PLL

locks to this user supplied 106.25

MHz byte clock. This clock is

then multiplied by 10, to generate

the 1062.5 MHz serial signal

clock used to generate the high-

speed output. The high-speed

outputs are capable of interfacing

directly to copper cables for

electrical transmission or to a

separate fiber-optic module for

optical transmission.

The receiver section accepts a

serial electrical data stream at

1062.5 MBd and recovers the

original 10-bit wide parallel data.

The receiver PLL locks onto the

incoming serial signal and

recovers the high-speed serial

clock and data. The serial data is

696

5965-8113E (4/97)

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