DLG1414 Ver la hoja de datos (PDF) - Siemens AG
Número de pieza
componentes Descripción
Fabricante
DLG1414 Datasheet PDF : 5 Pages
| |||
Figure 4. Block diagram
Rows 0 to 6
Row Control Logic
&
Row Drivers
Display
321 0
Columns 0 to 19
OSC
÷128
Counter
÷7
Counter
Timing and Control Logic
RAM Read Logic
D6
D5
7 Bit ASCII Code
D4
D3
D2
RAM
Memory
D1
D0
4 X 7 bit
Row Decoder
ROM
128 X 35 Bit
ASCII
Character
Decode
4480 bits
Column Data
Column Enable
Latches and
Column Drivers
WR
Write
A0
Address
A1
Decoder
Character Set
D0 0
10
1
0
1
01
0
1
0
1
0
1
0
1
ASCII D1 0
01
1
0
0
11
0
0
1
1
0
0
1
1
CODE D2 0
00
0
1
1
11
0
0
0
0
1
1
1
1
D3 0
00
0
0
0
00
1
1
1
1
1
1
1
1
D6 D5 D4 HEX 0
1
2
3
4
5
6
7
8
9A
BC
DE
F
000 0
001 1
010 2
011 3
100 4
101 5
110 6
111 7
1. High=1 level. 2. Low=0 level. 3. Upon power up, device will initialize in a random state.
2–4
DLR/DLO/DLG1414
Share Link: 