HFBR-5104 Ver la hoja de datos (PDF) - HP => Agilent Technologies

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HFBR-5104

FDDI, 100 Mbps ATM, and Fast Ethernet Transceivers in Low Cost 1x9 Package Style

HP => Agilent Technologies 

FDDI PMD and LCF-PMD

These transceivers are compat-

standards without violating the

ible with either industry standard

worst case output electrical jitter wave or hand solder processes.

allowed in the Tables E1 of the

Annexes E.

Shipping Container

The transceiver is packaged in a

The jitter specifications stated in shipping container designed to

the following 1300 nm

protect it from mechanical and

, transceiver specification tables

are derived from the values in

Tables E1 of Annexes E. They

represent the worst case jitter

contribution that the transceivers

are allowed to make to the overall

system jitter without violating the

Annex E allocation example. In

practice the typical contribution

ESD damage during shipment or

storage.

of the HP transceivers is well

below these maximum allowed

NO INTERNAL CONNECTION

amounts.

Board Layout - Decoupling

Circuit and Ground Planes

It is important to take care in the

layout of your circuit board to

achieve optimum performance

from these transceivers. Figure 7

provides a good example of a

schematic for a power supply

,decoupling circuit that works well

with these parts. It is further

recommended that a contiguous

NO INTERNAL CONNECTION

 Recommended Handling

Precautions

Hewlett-Packard recommends

that normal static precautions be

taken in the handling and

assembly of these transceivers to

prevent damage which may be

induced by electrostatic

discharge (ESD). The HFBR-

HFBR-510X

TOP VIEW

Rx

Rx Tx

Tx

VEE RD RD SD VCC VCC TD TD VEE

1

2

3

4

5

6

7

8

9

5100 series of transceivers meet

C1

C2

MIL-STD-883C Method 3015.4

Class 2 products.

TERMINATION

L1 L2

VCC

R2 R3

Care should be used to avoid

shorting the receiver data or

signal detect outputs directly to

ground without proper current

limiting impedance.

Solder and Wash Process

Compatibility

The transceivers are delivered

with protective process plugs

inserted into the duplex SC or

duplex ST connector receptacle.


,,
,

,
 AT PHY

DEVICE

INPUTS

VCC

R5 R7

C6

R6

R8

C3

C4

VCC FILTER

AT VCC PINS

TRANSCEIVER

R9

R10

R1

R4

C5

TERMINATION

AT TRANSCEIVER

INPUTS

RD RD SD

VCC

TD

TD

NOTES:

THE SPLIT-LOAD TERMINATIONS FOR ECL SIGNALS NEED TO BE LOCATED AT THE INPUT

OF DEVICES RECEIVING THOSE ECL SIGNALS. RECOMMEND 4-LAYER PRINTED CIRCUIT

This process plug protects the

BOARD WITH 50 OHM MICROSTRIP SIGNAL PATHS BE USED.

optical subassemblies during

wave solder and aqueous wash

R1 = R4 = R6 = R8 = R10 = 130 OHMS.

R2 = R3 = R5 = R7 = R9 = 82 OHMS.

C1 = C2 = C3 = C5 = C6 = 0.1 µF.

processing and acts as a dust

cover during shipping.

C4 = 10 µF.

L1 = L2 = 1 µH COIL OR FERRITE INDUCTOR.

Figure 7. Recommended Decoupling and Termination Circuits

132

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