CS5124XDR8 Ver la hoja de datos (PDF) - ON Semiconductor

Número de pieza

componentes Descripción

Fabricante

CS5124XDR8

High Performance, Integrated Current Mode PWM Controllers

ON Semiconductor 

CS5124, CS5126

SYNC (CS5126 ONLY)

VCC

UVLO

BIAS

(CS5124

ONLY)

VCC UVLO COMP

VCC

OSC

DIS

+

–

+

V 7.7 V/7.275 V

G2 VREF = 5.0 V

ENABLE

RAMP

V5REF

RQ

G1

F1

S

RESET DOMAIN

LINE UVLO COMP

–

–

VREFOK

+

+

V

85 mV/µs

170 mV/µs

G3

TSHUT

+

V5REF

–

150°C/125°C

+V

2.62 V/2.45 V

10 µA

+

VFB COMP

PWM COMP

+

V

(1/5)

490 mV 1/10

+

–

REMOTE

(SLEEP) COMP

+

V 1.91 V/1.83 V

SOFT START LATCH

–

+

+V

(125 mV)

+

60 mV

(525 mV)

2ND

–

+

275 mV

ICOMP V

÷

1000 Ω

F3

SQ

R

DRIVER

V5REF

G7

4500 Ω

GATE

VFB

ISENSE

F2

G5 S Q

VCC

R

LINE AMP

–

+

+

2.0 V V

2.9 R SET DOMAIN

–

R

+

SS COMP +

275 mV V

(2.65 V)

2.90 V

+

V

BLANK

G6

V5REF

BLANKING

SS AMP

+

–

GND

1.32 V

+

SS

V

Figure 2. Block Diagram

THEORY OF OPERATION

Powering the IC

VCC can be powered directly from a regulated supply and

requires 500 µA of start–up current. The CS5124/6 includes

a line bias pin (BIAS) that can be used to control a series pass

transistor for operation over a wide input voltage. The BIAS

pin will control the gate voltage of an N–channel MOSFET

placed between VIN and VCC to regulate VCC at 8.0 V.

VCC and UVLO Pins

The UVLO pin has three different modes; low power

shutdown, Line UVLO, and normal operation. To illustrate

how the UVLO pin works; assume that VIN, as shown in the

application schematic, is ramped up starting at 0 V with the

UVLO pin open. The SS and ISENSE pins also start at 0 V.

While the UVLO is below 1.8 V, the IC will remain in a low

current sleep mode and the BIAS pin of the CS5124 is

internally clamped to a maximum of 15 V. When the voltage

on the UVLO pin rises to between 1.8 V and 2.6 V the

reference for the VCC UVLO is enabled and VCC is

regulated to 8.0 V by the BIAS pin (CS5124 only), but the

IC remains in a UVLO state and the output driver does not

switch. When the UVLO pin exceeds 2.6 V and the VCC pin

exceeds 7.7 V, the GATE pin is released from a low state and

can begin switching based on the comparison of the ISENSE

and VFB pins. The Soft Start capacitor begins charging from

0 V at 10 µA. As the capacitor charges, a buffered version

of the capacitor voltage appears on the VFB pin and the VFB

voltage begins to rise. As VFB rises the duty cycle increases

until the supply comes into regulation.

Soft Start

Soft Start is accomplished by clamping the VFB pin 1.32 V

below the SS pin during normal start up and during restart

after a fault condition. When the CS5124/6 starts, the Soft

http://onsemi.com

6

Share Link: