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CS5124XDR8 Ver la hoja de datos (PDF) - ON Semiconductor

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CS5124XDR8 Datasheet PDF : 12 Pages
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CS5124, CS5126
ELECTRICAL CHARACTERISTICS (–40°C TJ 125°C; –40°C TA 105°C, 7.60 V VCC 20 V, UVLO = 3.0 V,
ISENSE = 0 V, CV(CC) = 0.33 µF, CGATE = 1.0 nF (ESR = 10 Ω); CSS = 470 pF; CV(FB) = 100 pF, unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
General
ICC Operating – VGATE not switching
ICC at VCC Low
VCC = 6.0 V
ICC Sleep
VUVL = 1.0 V
Low VCC Lockout
VCC Turn–on Threshold Voltage
VCC Turn–off Threshold Voltage
VCC Hysteresis
UVLO
10
13
500
750
210
275
7.2
7.7
8.3
6.8
7.3
7.8
350
425
500
Sleep Threshold Voltage
UVLO decreasing
1.5
1.8
2.3
Sleep Threshold Voltage
UVLO increasing
1.88
2.45
Sleep Hysteresis
35
85
150
UVLO Turn–off Threshold Voltage
Note 2
2.3
2.45
2.6
UVLO Turn–on Threshold Voltage
Note 2
2.50
2.63
2.76
UVLO Hysteresis
UVLO Hysteresis
UVLO Input Bias Current
Turn–on – Turn–off (–40°C TJ 100°C) Note 2
170
185
200
Turn–on – Turn–off (100°C TJ 125°C) Note 2
50
185
400
–1.0
1.0
UVLO Clamp
With UVLO sinking 1.0 mA
5.0
7.5
12
VCC Clamp and BIAS Pin
VCC Clamp Voltage
CS5124 Only. Connect an NFET as follows: BIAS = G, VCC = S, VIN = D.
36 V VIN 60 V, 200 nF CSS 500 nF,
R = 500 k
7.275
7.9
8.625
BIAS Minimum Voltage
BIAS Clamp
Measure Voltage on BIAS with:
1.6
2.8
4.0
10 V VCC 20 V & 50 µA IBIAS 1.0 mA
With BIAS pin sinking 1.0 mA
12
15
20
200 kHz Oscillator
CS5126 Only
Operating Frequency
175
200
225
Max Duty Cycle Clamp
78
82.5
85
Slope Compensation
(Normal operation)
12
18
23
Slope Compensation
(Synchronized operation)
Note 2
7.0
12
16
SYNC Input Threshold Voltage
1.0
2.0
3.0
SYNC Input Impedance
Measured with SYNC = 1.0 V & 10 V
50
120
230
400 kHz Oscillator
CS5124 Only
Operating Frequency
360
400
440
Max Duty Cycle Clamp
80.0
82.5
85.0
Slope Compensation
15
21
26
2. Not tested in production. Specification is guaranteed by design.
Unit
mA
µA
µA
V
V
mV
V
V
mV
V
V
mV
mV
µA
V
V
V
V
kHz
%
mV/µs
mV/µs
V
k
kHz
%
mV/µs
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