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Fabricante

IR3846

Single-Input Voltage, Synchronous Buck Regulator 35A Highly Integrated SupIRBuck®

International Rectifier 

IR3846

PIN DESCRIPTIONS

PIN #

1

2, 3, 22, 23, 26

4

5

6

7

8

9

10

11

12, 25

13

14

15

16

17

18

19

20

21

24

PIN NAME

PVin

NC

Boot

Enable

Rt/Sync

OCset

Vsns

FB

COMP

RSo

PGND

LGND

S_Ctrl

RS-

RS+

Vref

Vp

PGD

Vin

VCC/LDO_out

SW

PIN DESCRIPTION

Input voltage for power stage. Bypass capacitors between PVin and

PGND should be connected very close to this pin and PGND; also forms

input to feedforward block

No Connect

Supply voltage for high side driver

Enable pin to turning on and off the IC.

Use an external resistor from this pin to LGND to set the switching

frequency, very close to the pin. This pin can also be used for external

synchronization.

Current limit setpoint. This pin allows the trip point to be set to one of

three possible settings by either floating this pin, tying it to VCC or tying it

to PGnd.

Sense pin for OVP and PGood

Inverting input to the error amplifier. This pin is connected directly to the

output of the regulator or to the output of the remote sense amplifier, via

resistor divider to set the output voltage and provide feedback to the

error amplifier.

Output of error amplifier. An external resistor and capacitor network is

typically connected from this pin to FB to provide loop compensation.

Remote Sense Amplifier Output

Power ground. This pin should be connected to the system’s power

ground plane. Bypass capacitors between PVin and PGND should be

connected very close to PVIN pin (pin 1) and this pin.

Signal ground for internal reference and control circuitry.

Soft start/stop control. A high logic input enables the device to go into the

internal soft start; a low logic input enables the output soft discharged.

Pull this pin high if this function is not used.

Remote Sense Amplifier input. Connect to ground at the load.

Remote Sense Amplifier input. Connect to output at the load.

External reference voltage can be used for margining operation. A

capacitor between 100pF and 180pF should be connected between this

pin and LGnd. Tie to LGnd for tracking function.

Used for voltage sequencing and tracking. Leave open if sequencing or

tracking is not needed, ensuring that there is no capacitor on the pin.

Power Good status pin. Output is open drain. Connect a pull up resistor

from this pin to VCC.

Input Voltage for LDO.

Bias Voltage for IC and driver section, output of LDO. Add a minimum of

4.7uF bypass cap from this pin to PGnd.

Switch node. This pin is connected to the output inductor.

4 www.irf.com © 2013 International Rectifier

August 01, 2013

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